Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 21
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 V
REF
0.6
HSTL, Class I, 1.5V HSTL_I 50 0 V
REF
0.75
HSTL, Class II, 1.5V HSTL_II 25 0 V
REF
0.75
HSTL, Class I, 1.8V HSTL_I_18 50 0 V
REF
0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 V
REF
0.9
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 V
REF
0.6
SSTL12, 1.2V SSTL12 50 0 V
REF
0.6
SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 V
REF
0.675
SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 V
REF
0.75
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
SSTL18_I, SSTL18_II 50 0 V
REF
0.9
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 V
REF
0.9
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 V
REF
0.6
DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 V
REF
0.75
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 V
REF
0.9
DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 V
REF
0.6
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 V
REF
0.675
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 V
REF
0.75
DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 V
REF
0.9
LVDS, 2.5V LVDS_25 100 0 0
(2)
0
BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0
(2)
0
Mini LVDS, 2.5V MINI_LVDS_25 100 0 0
(2)
0
PPDS_25 PPDS_25 100 0 0
(2)
0
RSDS_25 RSDS_25 100 0 0
(2)
0
TMDS_33 TMDS_33 50 0 0
(2)
3.3
Notes:
1. C
REF
is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
Table 20: Output Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute
R
REF
(Ω)
C
REF
(1)
(pF)
V
MEAS
(V)
V
REF
(V)