Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 20
Output Delay Measurements
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay
of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure 1 and Figure 2.
Parameters V
REF
, R
REF
, C
REF
, and V
MEAS
fully describe the test conditions for each I/O standard. The most accurate prediction
of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 20.
2. Record the time to V
MEAS
.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance
value to represent the load.
4. Record the time to V
MEAS
.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the
PCB trace.
X-Ref Target - Figure 1
Figure 1: Single-Ended Test Setup
X-Ref Target - Figure 2
Figure 2: Differential Test Setup
Table 20: Output Delay Measurement Methodology
Description I/O Standard Attribute
R
REF
(Ω)
C
REF
(1)
(pF)
V
MEAS
(V)
V
REF
(V)
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0
LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0
LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0
LVTTL, 3.3V LVTTL 1M 0 1.65 0
PCI33, 3.3V PCI33_3 25 10 1.65 0
V
REF
R
REF
V
MEAS
(Voltage Level When Taking
Delay Measurement)
C
REF
(Probe Capacitance)
FPGA Output
DS181_04_090514
R
REF
V
MEAS
+
–
C
REF
FPGA Output
DS181_05_090514