Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 19
HSTL, Class I & II, 1.5V HSTL_I, HSTL_II V
REF
–0.65 V
REF
+0.65 V
REF
0.75
HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 V
REF
–0.8 V
REF
+0.8 V
REF
0.90
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
SSTL, 1.35V SSTL135, SSTL135_R V
REF
– 0.575 V
REF
+ 0.575 V
REF
0.675
SSTL, 1.5V SSTL15, SSTL15_R V
REF
–0.65 V
REF
+0.65 V
REF
0.75
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II V
REF
–0.8 V
REF
+0.8 V
REF
0.90
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9 – 0.125 0.9 + 0.125 0
(5)
–
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.125 0.6 + 0.125 0
(5)
–
DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125 0
(5)
–
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125 0.9 + 0.125 0
(5)
–
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.125 0.6 + 0.125 0
(5)
–
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135,
DIFF_SSTL135_R
0.675 – 0.125 0.675 + 0.125 0
(5)
–
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125 0
(5)
–
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125 0
(5)
–
LVDS_25, 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0
(5)
–
BLVDS_25, 2.5V BLVDS_25 1.25 – 0.125 1.25 + 0.125 0
(5)
–
MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25 – 0.125 1.25 + 0.125 0
(5)
–
PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0
(5)
–
RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0
(5)
–
TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0
(5)
–
Notes:
1. Input waveform switches between V
L
and V
H
.
2. Measurements are made at typical, minimum, and maximum V
REF
values. Reported delays reflect worst case of these measurements. V
REF
values listed are typical.
3. Input voltage level from which measurement starts.
4. This is an input voltage reference that bears no relation to the V
REF
/ V
MEAS
parameters found in IBIS models and/or noted in Figure 1.
5. The value given is the differential input voltage.
Table 19: Input Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute V
L
(1)
V
H
(1)
V
MEAS
(3)(5)
V
REF
(2)(4)