Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 18
Table 18 specifies the values of T
IOTPHZ
and T
IOIBUFDISABLE
. T
IOTPHZ
is described as the delay from the T pin to the IOB pad through the
output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). T
IOIBUFDISABLE
is described as the IOB delay from
IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than T
IOTPHZ
when the
INTERMDISABLE pin is used.
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 19 shows the test setup parameters used for measuring input delay.
SSTL135_F 0.67 0.75 0.82 0.88 0.82 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns
SSTL15_F 0.60 0.68 0.75 0.75 0.75 0.80 1.07 1.19 1.45 1.45 1.45 1.68 1.09 1.22 1.46 1.46 1.46 1.31 ns
SSTL18_I_F 0.67 0.75 0.82 0.86 0.82 0.87 1.12 1.24 1.49 1.53 1.49 1.72 1.13 1.27 1.51 1.54 1.51 1.36 ns
SSTL18_II_F 0.67 0.75 0.82 0.88 0.82 0.85 1.12 1.24 1.49 1.51 1.49 1.71 1.13 1.27 1.51 1.52 1.51 1.34 ns
DIFF_SSTL135
_F
0.68 0.76 0.83 0.88 0.83 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns
DIFF_SSTL15_F 0.68 0.76 0.83 0.88 0.83 0.87 1.07 1.19 1.45 1.45 1.45 1.68 1.09 1.22 1.46 1.46 1.46 1.31 ns
DIFF_SSTL18_I
_F
0.71 0.79 0.86 0.88 0.86 0.87 1.23 1.35 1.60 1.60 1.60 1.80 1.24 1.38 1.62 1.62 1.62 1.44 ns
DIFF_SSTL18_II
_F
0.71 0.79 0.86 0.88 0.86 0.87 1.21 1.33 1.59 1.59 1.59 1.79 1.23 1.36 1.60 1.60 1.60 1.42 ns
Table 18: IOB 3-state Output Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
T
IOTPHZ
T input to pad high-impedance 2.06 2.19 2.37 2.37 2.37 2.03 ns
T
IOIBUFDISABLE
IBUF turn-on time from IBUFDISABLE to O
output
2.11 2.30 2.60 2.60 2.60 2.17 ns
Table 19: Input Delay Measurement Methodology
Description I/O Standard Attribute V
L
(1)
V
H
(1)
V
MEAS
(3)(5)
V
REF
(2)(4)
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 –
LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 –
LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 –
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 –
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 –
LVTTL, 3.3V LVTTL 0.1 3.2 1.65 –
MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9 –
PCI33, 3.3V PCI33_3 0.1 3.2 1.65 –
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
T
IOPI
T
IOOP
T
IOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3
-2/
-2LE
-1
-1Q/
-1M
-1LI -2LE -3
-2/
-2LE
-1
-1Q/
-1M
-1LI -2LE -3
-2/
-2LE
-1
-1Q/
-1M
-1LI -2LE