Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 14
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Artix-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to
the same guidelines as the AC Switching Characteristics, page 11.
Table 15: Networking Applications Interface Performances
Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) 680 680 600 600 600 Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) 1250 1250 950 950 950 Mb/s
SDR LVDS receiver (SFI-4.1)
(1)
680 680 600 600 600 Mb/s
DDR LVDS receiver (SPI-4.2)
(1)
1250 1250 950 950 950 Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
Table 16: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator
(1)(2)
Memory Standard
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
4:1 Memory Controllers
DDR3 1066 800 800 667 800 800 Mb/s
DDR3L 800 800 667 N/A 667 667 Mb/s
DDR2 800 800 667 533 667 667 Mb/s
2:1 Memory Controllers
DDR3 800 700 620 620 620 620 Mb/s
DDR3L 800 700 620 N/A 620 620 Mb/s
DDR2 800 700 620 533 620 620 Mb/s
LPDDR2 667 667 533 400 533 533 Mb/s
Notes:
1. V
REF
tracking is required. For more information, see 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
2. When using the internal V
REF
, the maximum data rate is 800 Mb/s (400 MHz).