Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.21) September 27, 2016 Product Specification Introduction Artix®-7 FPGAs are available in -3, -2, -1, -1LI, and -2L speed grades, with -3 having the highest performance. The Artix-7 FPGAs predominantly operate at a 1.0V core voltage. The -1LI and -2L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 and -2 devices, respectively.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating – 14 mA IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT – 12 mA IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND – 6.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 2: Recommended Operating Conditions(1)(2) (Cont’d) Symbol VREFP Description Min Typ Max Units 1.20 1.25 1.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d) Symbol Description Min Typ(1) Max Units n Temperature diode ideality factor – 1.010 – – r Temperature diode series resistance – 2 – Ω Notes: 1. 2. 3. 4. Typical values are specified at nominal voltage, 25°C. This measurement represents the die capacitance at the pad, not including the package. Maximum value specified for worst case process at 25°C.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current Speed Grade Symbol ICCINTQ ICCOQ Description Quiescent VCCINT supply current Quiescent VCCO supply current DS181 (v1.21) September 27, 2016 Product Specification Device 1.0V 0.95V 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current (Cont’d) Speed Grade Symbol ICCAUXQ Description Quiescent VCCAUX supply current ICCBRAMQ Quiescent VCCBRAM supply current Device 1.0V 0.95V 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 7: Power Supply Ramp Time Symbol Description Conditions Min Max Units TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms TVCCBRAM Ramp time from GND to 90% of VCCBRAM ms TVCCO2VCCAUX Allowed time per power cycle for VCCO – VCCAUX > 2.625V 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 8: SelectIO DC Input and Output Levels(1)(2) (Cont’d) VIL I/O Standard SSTL18_II VIH V, Min V, Max V, Min V, Max –0.300 VREF – 0.125 VREF + 0.125 VOL VOH IOL V, Max V, Min IOH mA, Max mA, Min VCCO + 0.300 VCCO/2 – 0.600 VCCO/2 + 0.600 13.40 –13.40 Notes: 1. 2. 3. 4. 5. 6. Tested according to relevant specifications. 3.3V and 2.5V standards are only supported in HR I/O banks.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics LVDS DC Specifications (LVDS_25) Table 11: LVDS_25 DC Specifications(1) Symbol DC Parameter Conditions Min Typ Max Units 2.375 2.500 2.625 V VCCO Supply Voltage VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals – – 1.675 V VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics AC Switching Characteristics All values represented in this data sheet are based on the speed specifications from the ISE® Design Suite 14.7 and Vivado® Design Suite 2016.3 as outlined in Table 12. Table 12: Artix-7 FPGA Speed Specification Version By Device Version In: Typical VCCINT Device ISE 14.7 Vivado 2016.3 (Table 2) N/A 1.15 1.0V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T N/A 1.15 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Speed Grade Designations Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Artix-7 device on a per speed grade basis.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 14: Artix-7 Device Production Software and Speed Specification Release (Cont’d) Speed Grade Device 1.0V -3 -2 -2LE -1 0.95V 0.9V -2LE -1Q -1M -1LI XC7A100T ISE tools 14.4 or Vivado tools 2012.4 with the 14.4/2012.4 device pack v1.07 N/A N/A Vivado tools 2014.4 v1.14 XC7A200T ISE tools 14.4 or Vivado tools 2012.4 with the 14.4/2012.4 device pack v1.07 N/A N/A Vivado tools 2014.4 v1.14 ISE tools 14.5 or Vivado tools 2013.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Artix-7 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 11. Table 15: Networking Applications Interface Performances Speed Grade Description 1.0V 0.95V 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics IOB Pad Input/Output/3-State Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. • TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V -3 -2/ -2LE 0.95V 0.9V -1 -1Q/ -1M -1LI -2LE 1.0V -3 -2/ -2LE -1 0.95V 0.9V -1Q/ -1M -1LI -2LE 0.95V 0.9V Units 1.0V -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE HSTL_I_S 0.67 0.75 0.82 0.86 0.82 0.87 1.62 1.74 1.99 1.99 1.99 2.19 1.63 1.77 2.01 2.01 2.01 1.83 ns HSTL_II_S 0.65 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V -2/ -2LE 0.95V 0.9V -1 -1Q/ -1M -1LI -2LE LVCMOS18_S16 0.74 0.83 0.89 0.97 0.89 LVCMOS18_S24 0.74 0.83 0.89 0.97 LVCMOS18_F4 0.74 0.83 0.89 LVCMOS18_F8 -3 1.0V -2/ -2LE 0.95V 0.9V -1Q/ -1M 0.95V 0.9V Units 1.0V -2/ -2LE -1Q/ -1M -1LI -2LE 0.94 1.52 1.65 1.90 1.90 1.90 2.13 1.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V -3 -2/ -2LE 0.95V 0.9V -1 -1Q/ -1M -1LI -2LE 1.0V -3 -2/ -2LE -1 0.95V 0.9V -1Q/ -1M -1LI -2LE 0.95V 0.9V Units 1.0V -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE SSTL135_F 0.67 0.75 0.82 0.88 0.82 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns SSTL15_F 0.60 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 19: Input Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute VL (1) VH(1) VMEAS VREF (3)(5) (2)(4) HSTL, Class I & II, 1.5V HSTL_I, HSTL_II VREF – 0.65 VREF + 0.65 VREF 0.75 HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF – 0.8 VREF + 0.8 VREF 0.90 HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 VREF – 0.5 VREF + 0.5 VREF 0.60 SSTL (Stub Terminated Transceiver Logic), 1.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Output Delay Measurements Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 20: Output Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 VREF 0.6 HSTL, Class I, 1.5V HSTL_I 50 0 VREF 0.75 HSTL, Class II, 1.5V HSTL_II 25 0 VREF 0.75 HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input/Output Logic Switching Characteristics Table 21: ILOGIC Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Units Setup/Hold TICE1CK/ TICKCE1 CE1 pin setup/hold with respect to CLK 0.48/0.02 0.54/0.02 0.76/0.02 0.76/0.02 0.76/0.02 0.50/–0.07 ns TISRCK/ TICKSR SR pin setup/hold with respect to CLK 0.60/0.01 0.70/0.01 1.13/0.01 1.13/0.01 1.13/0.01 0.88/–0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 22: OLOGIC Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1Q/-1M -1LI -2LE 0.83 0.96 1.16 1.16 1.16 1.36 ns Combinatorial TODQ D1 to OQ out or T1 to TQ out Sequential Delays TOCKQ CLK to OQ/TQ out 0.47 0.49 0.56 0.56 0.56 0.63 ns TRQ_OLOGIC SR pin to OQ/TQ out 0.72 0.80 0.95 0.95 0.95 1.12 ns 7.60 7.60 10.51 10.51 10.51 11.39 ns 0.64 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Output Serializer/Deserializer Switching Characteristics Table 24: OSERDES Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE 0.45/0.03 0.63/0.03 0.63/0.08 0.63/0.03 Units Setup/Hold TOSDCK_D/ TOSCKD_D D input setup/hold with respect to CLKDIV 0.42/0.03 0.44/–0.02 ns TOSDCK_T/ TOSCKD_T(1) T input setup/hold with respect to CLK 0.69/–0.13 0.73/–0.13 0.88/–0.13 0.88/–0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input/Output Delay Switching Characteristics Table 25: Input/Output Delay Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1Q/-1M -1LI -2LE 3.67 3.67 3.67 3.67 3.67 3.67 µs IDELAYCTRL TDLYCCO_RDY Reset to ready for IDELAYCTRL FIDELAYCTRL_REF Attribute REFCLK frequency = 200.00(1) 200.00 200.00 200.00 200.00 200.00 200.00 MHz Attribute REFCLK frequency = 300.00(1) 300.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 26: IO_FIFO Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Units IO_FIFO Clock to Out Delays TOFFCKO_DO RDCLK to Q outputs 0.55 0.60 0.68 0.68 0.68 0.81 ns TCKO_FLAGS Clock to IO_FIFO flags 0.55 0.61 0.77 0.77 0.77 0.79 ns 0.51/0.02 0.58/0.02 0.58/0.18 0.58/0.02 Setup/Hold TCCK_D/TCKC_D D inputs to WRCLK 0.47/0.02 0.76/0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics CLB Switching Characteristics Table 27: CLB Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Units Combinatorial Delays TILO An – Dn LUT address to A 0.10 0.11 0.13 0.13 0.13 0.15 ns, Max TILO_2 An – Dn LUT address to AMUX/CMUX 0.27 0.30 0.36 0.36 0.36 0.41 ns, Max TILO_3 An – Dn LUT address to BMUX_A 0.42 0.46 0.55 0.55 0.55 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 28: CLB Distributed RAM Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Units Sequential Delays TSHCKO Clock to A – B outputs 0.98 1.09 1.32 1.32 1.32 1.54 ns, Max TSHCKO_1 Clock to AMUX – BMUX outputs 1.37 1.53 1.86 1.86 1.86 2.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Block RAM and FIFO Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Clock CLK to DOUT output (without output register)(2)(3) 1.85 2.13 2.46 2.46 2.46 2.87 ns, Max Clock CLK to DOUT output (with output register)(4)(5) 0.64 0.74 0.89 0.89 0.89 1.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V -2LE -3 -2/-2LE -1 -1Q/-1M -1LI Units TRDCK_DI_ECC/ TRCKD_DI_ECC DIN inputs with block RAM ECC in standard mode(9) 0.50/0.43 0.55/0.46 0.63/0.50 0.63/0.50 0.63/0.50 0.78/0.54 ns, Min TRDCK_DI_ECCW/ TRCKD_DI_ECCW DIN inputs with block RAM ECC encode only(9) 0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 1.17/0.50 1.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Units FMAX_CAS_WF_NC Block RAM cascade (write first, no change mode) when cascade but not in RF mode 467.07 418.59 345.78 345.78 345.78 273.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DSP48E1 Switching Characteristics Table 31: DSP48E1 Switching Characteristics Speed Grade Symbol Description 1.0V -3 0.95V 0.9V -2/-2LE -1 -1Q/-1M -1LI -2LE Units Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK 0.26/ 0.12 0.30/ 0.13 0.37/ 0.14 0.37/ 0.28 0.37/ 0.14 0.45/ 0.14 ns TDSPDCK_B_BREG/ TDSPCKD_B_BREG B input to B register CLK 0.33/ 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 31: DSP48E1 Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Units Setup and Hold Times of the RST Pins TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG} {RSTA, RSTB} input to {A, B} register CLK 0.41/ 0.11 0.46/ 0.13 0.55/ 0.15 0.55/ 0.24 0.55/ 0.15 0.63/ 0.40 ns TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG RSTC input to C register CLK 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 31: DSP48E1 Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Units Clock to Outs from Output Register Clock to Output Pins TDSPCKO_P_PREG CLK PREG to P output 0.33 0.37 0.44 0.44 0.44 0.54 ns TDSPCKO_CARRYCASCOUT_PREG CLK PREG to CARRYCASCOUT output 0.52 0.59 0.69 0.69 0.69 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 31: DSP48E1 Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V -3 -2/-2LE -1 0.95V 0.9V -1LI -2LE -1Q/-1M Units FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG) 260.01 227.01 190.69 190.69 190.69 150.13 MHz FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect 241.72 211.15 177.43 177.43 177.43 140.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 34: Regional Clock Buffer Switching Characteristics (BUFR) (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1Q/-1M -1LI -2LE 420.00 375.00 315.00 315.00 315.00 315.00 MHz 0.95V 0.9V Units Maximum Frequency FMAX_BUFR(1) Regional clock tree (BUFR) Notes: 1. The maximum input frequency to the BUFR and BUFMR is the BUFIO FMAX frequency.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 36: Duty Cycle Distortion and Clock-Tree Skew (Cont’d) Speed Grade Symbol TDCD_BUFR Description Device Regional clock tree duty cycle distortion All 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE 0.18 0.18 0.18 0.18 0.18 0.18 Units ns Notes: 1. 2. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 37: MMCM Specification (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1LI -2LE 5.00 5.00 5.00 5.00 5.00 ns MMCM_RSTMINPULSE Minimum reset pulse width MMCM_FPFDMAX Maximum frequency at the phase frequency detector 550.00 500.00 450.00 450.00 450.00 MHz MMCM_FPFDMIN Minimum frequency at the phase frequency detector 10.00 10.00 10.00 10.00 10.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics PLL Switching Characteristics Table 38: PLL Specification Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE Units PLL_FINMAX Maximum input clock frequency 800.00 800.00 800.00 800.00 800.00 MHz PLL_FINMIN Minimum input clock frequency 19.00 19.00 19.00 19.00 19.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 38: PLL Specification (Cont’d) Speed Grade Symbol FDCK Description 1.0V DCLK frequency 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE 200.00 200.00 200.00 200.00 100.00 Units MHz, Max Notes: 1. 2. 3. 4. 5. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any PLL outputs with identical phase.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1) Speed Grade Symbol Description Device 1.0V -3 -2/-2LE -1 -1M/-1Q 0.95V 0.9V -1LI -2LE Units SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 41: Clock-Capable Clock Input to Output Delay With MMCM Speed Grade Symbol Description Device 1.0V -3 -2/-2LE -1 -1M/-1Q 0.95V 0.9V -1LI -2LE Units SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM XC7A12T 1.00 1.00 1.00 N/A 1.00 ns XC7A15T 1.00 1.00 1.00 N/A 1.00 XC7A25T 1.00 1.00 1.00 N/A 1.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 42: Clock-Capable Clock Input to Output Delay With PLL Speed Grade Symbol Description Device 1.0V -3 -2/-2LE -1 -1M/-1Q 0.95V 0.9V -1LI -2LE Units SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. TICKOFPLLCC Clock-capable clock input and OUTFF with PLL XC7A12T 0.83 0.83 0.83 N/A 0.83 ns XC7A15T 0.82 0.82 0.82 N/A 0.82 XC7A25T 0.83 0.83 0.83 N/A 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted. Table 44: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks Speed Grade Symbol Description Device 1.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 45: Clock-Capable Clock Input Setup and Hold With MMCM Speed Grade Symbol Description Device 1.0V -3 -2/-2LE Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 TPSMMCMCC/ TPHMMCMCC No delay clockcapable clock input and IFF(2) with MMCM -1 0.95V 0.9V -1M/-1Q -1LI -2LE Units Standard.(1) XC7A12T 2.37/–0.61 2.69/–0.61 3.21/–0.61 N/A 3.21/–0.61 ns XC7A15T 2.46/–0.62 2.80/–0.62 3.35/–0.62 N/A 3.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 46: Clock-Capable Clock Input Setup and Hold With PLL Speed Grade Symbol Description Device 1.0V -3 -2/-2LE -1 Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 TPSPLLCC/ TPHPLLCC -1M/-1Q 0.95V 0.9V -1LI -2LE Units Standard.(1) No delay clock-capable XC7A12T clock input and IFF(2) XC7A15T with PLL XC7A25T 2.68/–0.19 3.04/–0.19 3.63/–0.19 N/A 3.63/–0.19 ns 2.77/–0.20 3.15/–0.20 3.77/–0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 48: Sample Window (Cont’d) Speed Grade Symbol TSAMP_BUFIO Description 1.0V Sampling error at receiver pins using BUFIO(2) 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE 0.35 0.40 0.46 0.46 0.46 0.46 Units ns Notes: 1. 2. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and process.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 49: Package Skew (Cont’d) Symbol TPKGSKEW Description Package skew(1) Device XC7A100T XC7A200T Package Value Units CSG324 113 ps FTG256 120 ps FGG484 144 ps FGG676 153 ps SBG484/SBV484 111 ps FBG484/FBV484 109 ps FBG676/FBV676 121 ps FFG1156/FFV1156 151 ps CPG236 48 ps CSG324 104 ps CSG325 142 ps CPG236 48 ps CSG324 104 ps CSG325 142 ps CPG236 48 ps CSG324 104 ps CSG325 142 ps CSG324
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 50: GTP Transceiver DC Specifications (Cont’d) Symbol VCMOUTAC DC Parameter Conditions Min Typ Common mode output voltage: AC coupled TOSKEW Max 1/2 VMGTAVTT Units mV Transmitter output pair (TXP and TXN) intra-pair skew (FF, FB, SB packages) – – 10 ps Transmitter output pair (TXP and TXN) intra-pair skew (FG, FT, CS, CP packages) – – 12 ps DVPPIN Differential peak-to-peak input voltage External AC coupled 150 – 200
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics GTP Transceiver Switching Characteristics Consult 7 Series FPGAs GTP Transceiver User Guide (UG482) for further information. Table 52: GTP Transceiver Performance Speed Grade -3 (1.0V) Symbol Output Divider Description -1 (1.0V) -1LI (0.95V) -1Q (1.0V) -1M (1.0V) -2 (1.0V) -2LE (1.0V) -2LE (0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 55: GTP Transceiver PLL/Lock Time Adaptation Symbol TLOCK TDLOCK Description All Speed Grades Conditions Initial PLL lock Clock recovery phase acquisition and adaptation time. After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. Units Min Typ Max – – 1 ms – 50,000 2.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 57: GTP Transceiver Transmitter Switching Characteristics Symbol Description FGTPTX Serial data rate range TRTX TX rise time TFTX TX fall time Condition Min Typ Max Units 0.500 – FGTPMAX Gb/s 20%–80% – 50 – ps 80%–20% ps – 50 – TLLSKEW TX lane-to-lane skew(1) – – 500 ps VTXOOBVDPP Electrical idle amplitude – – 20 mV TTXOOBTRANSITION Electrical idle transition time – – 140 ns – – 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 58: GTP Transceiver Receiver Switching Characteristics Symbol Description RX oversampler not enabled Min Typ Max Units 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics GTP Transceiver Protocol Jitter Characteristics For Table 59 through Table 63, the 7 Series FPGAs GTP Transceiver User Guide (UG482) contains recommended settings for optimal usage of protocol specific characteristics. Table 59: Gigabit Ethernet Protocol Characteristics Description Line Rate (Mb/s) Min Max Units 1250 – 0.24 UI 1250 0.749 – UI Line Rate (Mb/s) Min Max Units 3125 – 0.35 UI 3125 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 63: CPRI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units 614.4 – 0.35 UI 1228.8 – 0.35 UI 2457.6 – 0.35 UI 3072.0 – 0.35 UI 4915.2 – 0.3 UI 6144.0 – 0.3 UI 614.4 0.65 – UI 1228.8 0.65 – UI 2457.6 0.65 – UI 3072.0 0.65 – UI 4915.2(1) 0.60 – UI 6144.0(1) 0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics XADC Specifications Table 65: XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units VCCADC = 1.8V ± 5%, VREFP = 1.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 65: XADC Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units 1.20 1.25 1.30 V Ground VREFP pin to AGND, –40°C ≤ Tj ≤ 100°C 1.2375 1.25 1.2625 V Ground VREFP pin to AGND, –55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C 1.225 1.25 1.275 V XADC Reference(5) External Reference VREFP On-Chip Reference Externally supplied reference voltage Notes: 1. 2. 3. 4. 5.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 66: Configuration Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE 100.00 100.00 100.00 100.00 70.00 Units Internal Configuration Access Port FICAPCK Internal configuration access port (ICAPE2) clock frequency MHz, Max Master/Slave Serial Mode Programming Switching TDCCK/ TCCKD DIN setup/hold TCCO DOUT clock to out 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 66: Configuration Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE 100.00 100.00 100.00 100.00 70.00 Units Device DNA Access Port FDNACK DNA access port (DNA_PORT) MHz, Max Notes: 1. 2. To support longer delays in configuration, use the design solutions described in 7 Series FPGA Configuration User Guide (UG470).
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Date Version Description 06/01/2012 1.3 Reorganized entire data sheet including adding Table 43 and Table 47. Updated TSOL in Table 1. Updated IBATT and added RIN_TERM to Table 3. Updated Power-On/Off Power Supply Sequencing section with regards to GTP transceivers. In Table 8, updated many parameters including SSTL135 and SSTL135_R. Removed VOX column and added DIFF_HSUL_12 to Table 10. Updated VOL in Table 11.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Date Version Description 01/07/2014 1.9 In Table 13, promoted all XC7A75T speed grades from Advance to Production and all XQ7A50T speed grades from Preliminary to Advance. In Table 14, inserted “Vivado tools 2013.3” for the production XC7A75T speed grades. 01/23/2014 1.10 Updated the AC Switching Characteristics based upon ISE 14.7 and Vivado 2013.4. Updated Note 5 in Table 2. Removed pad pull-down @ VIN = 1.8V for IRPD in Table 3.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Date Version Description 11/19/2014 1.17 Replaced -2L speed grade with -2LE throughout. Updated descriptions of VCCINT and VCCBRAM in Table 2. Updated the AC Switching Characteristics based upon Vivado 2014.4. In Table 12, updated Vivado software version and added a row for VCCINT = 0.95V. In Table 13, moved all speed grades for all devices from Advance to Production. In Table 14, added Vivado 2014.4 software version to -1LI (0.