300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com Nexys4 DDR™ FPGA Board Reference Manual Nexys4 DDR rev. C; Revised September 11, 2014 1 Overview The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx®.
Nexys4 DDR™ FPGA Board Reference Manual Figure 1. Nexys4 DDR board features.
Nexys4 DDR™ FPGA Board Reference Manual 1.1 Migrating from Nexys4 The Nexys4 DDR is an incremental update to the Nexys4 board. The major improvement is the replacement of the 16 MiB CellularRAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that wraps the complexity of a DDR2 controller and is backwards compatible with the asynchronous SRAM interface of the CellularRAM, with certain limitations. See the Nexys4 DDR page at www.digilentinc.com for updates.
Nexys4 DDR™ FPGA Board Reference Manual least 1A of current (i.e., at least 5W of power). Many suitable supplies can be purchased from Digilent, through Digi-Key, or other catalog vendors. An external battery pack can be used by connecting the battery’s positive terminal to the center pin of JP3 and the negative terminal to the pin labeled J12, directly below JP3. Since the main regulator on the Nexys4 DDR cannot accommodate input voltages over 5.5VDC, an external battery pack must be limited to 5.5VDC.
Nexys4 DDR™ FPGA Board Reference Manual USB-JTAG/UART Port Micro-AB USB Connector (J6) 6-pin JTAG Header (J10) USB Controller JTAG Port 1x6 JTAG Header SPI Quad mode Flash Mode (JP1) Artix-7 M0 M2 M1 Micro SD Connector (J1) Type A USB Host Connector (J5) SPI Port User I/O Done 2 PIC24 Serial Prog. Port Prog JP2 JP1 NA SPI Flash NA JTAG USB MicroSD Programming Mode Media Select (JP2) Figure 3. Nexys4 DDR configuration options.
Nexys4 DDR™ FPGA Board Reference Manual setting (seen in Figure 3) is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs. Programming the Nexys4 DDR with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Lab Tools version of Vivado. The demonstration project available at www.digilentinc.
Nexys4 DDR™ FPGA Board Reference Manual In case of an error during configuration, the LED will blink rapidly. When the FPGA has been successfully configured, the behavior of the LED is application-specific. For example, if a USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard. 4 Memory The Nexys4 DDR board contains two external memories: a 1Gib (128MiB) DDR2 SDRAM and a 128Mib (16MiB) non-volatile serial Flash device.
Nexys4 DDR™ FPGA Board Reference Manual The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Digilent website to speed up the process. For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586)1. 4.
Nexys4 DDR™ FPGA Board Reference Manual Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details. EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII.
Nexys4 DDR™ FPGA Board Reference Manual clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Project Navigator or Core Generator tools. 7 USB-UART Bridge (Serial Port) The Nexys4 DDR includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that allows you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from www.ftdichip.
Nexys4 DDR™ FPGA Board Reference Manual SD MICRO (J1) SD/USB (JP2) 2 HOST (J5) microSD User I/O 7 FPGA Config PS2_CLK PS2_DAT FPGA Config F4 B2 PIC24FJ128 Artix-7 Figure 7. Nexys4 DDR PIC24 connections. 8.1 HID Controller The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores.
Nexys4 DDR™ FPGA Board Reference Manual 8.2 Keyboard PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every 100ms. When a key is released, an F0 key-up code is sent, followed by the scan code of the released key.
Nexys4 DDR™ FPGA Board Reference Manual 8.3 Mouse Once entered in stream mode and data reporting is enabled, the mouse outputs a clock and data signal when it is moved; otherwise, these signals remain at logic ‘1.’ Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device, as shown in Figure 10. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit.
Nexys4 DDR™ FPGA Board Reference Manual 9 VGA Port The Nexys4 DDR board uses 14 FPGA signals to create a VGA port with 4 bits-per-color and the two standard sync signals (HS – Horizontal Sync, and VS – Vertical Sync). The color signals use resistor-divider circuits that work in conjunction with the 75-ohm termination resistance of the VGA display to create 16 signal levels each on the red, green, and blue VGA signals.
Nexys4 DDR™ FPGA Board Reference Manual Anode (entire screen) Cathode ray tube Deflection coils Grid Electron guns (Red, Blue, Green) Cathode ray R,G,B signals (to guns) VGA cable High voltage supply deflection grid (>20kV) control control gun control Figure 12. Color CRT display. Electron beams emanate from “electron guns,” which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a “grid.
Nexys4 DDR™ FPGA Board Reference Manual pixel 0,0 pixel 0,639 640 pixels per row are displayed during forward beam trace Retrace - no information displayed during this time Display Surface pixel 479,0 pixel 479,639 Stable current ramp - information is displayed during this time Current waveform through horizontal defletion coil displays use from 240 to 1200 rows and from 320 to 1600 columns. The overall size of a display and the number of rows and columns determines the size of each pixel.
Nexys4 DDR™ FPGA Board Reference Manual counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation. HS Zero Detect Pixel CLK Horizontal Counter Set Horizontal Synch 3.84us Detect CE Zero Detect Vertical Synch Vertical Counter Reset Set 64us Detect VS Reset Figure 15.
Nexys4 DDR™ FPGA Board Reference Manual 3.3V P17 BTNL Buttons M17 BTNR M18 BTNU P18 BTND N17 BTNC 3.3V J15 SW0 L16 SW1 Slide Switches 1.8V SW2 M13 SW3 R15 SW4 R17 SW5 T18 SW6 U18 SW7 R13 SW8 T8 SW9 U8 SW10 R16 SW11 T13 SW12 H6 SW13 U12 SW14 U11 SW15 V10 H17 K15 J13 N14 R18 V17 U17 U16 V16 T15 U14 T16 V15 V14 V12 V11 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LEDs LD9 LD10 LD11 LD12 LD13 LD14 LD15 3.
Nexys4 DDR™ FPGA Board Reference Manual The sixteen individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible indicate power-on, FPGA programming status, and USB and Ethernet port status. 10.
Nexys4 DDR™ FPGA Board Reference Manual A scanning display controller circuit can be used to show an eight-digit number on this display. This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession at an update rate that is faster than the human eye can detect.
Nexys4 DDR™ FPGA Board Reference Manual 11 Pmod Connectors The Pmod connectors are arranged in a 2x6 right-angle, and are 100-mil female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 20. The VCC and Ground pins can deliver up to 1A of current.
Nexys4 DDR™ FPGA Board Reference Manual XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.
Nexys4 DDR™ FPGA Board Reference Manual communication is a read (1) or a write (0). Once specifications are made for communication, a data transfer takes place. For ADT7420, the data transfer should consist of the address of the desired device register followed by the data to be written to the specified register. To read from a register, the master must write the desired register address to the ADT7420, then send an I2C restart condition, and send a new read request to the ADT7420.
Nexys4 DDR™ FPGA Board Reference Manual INT1 B13 INT1: Interrupt One INT2 C16 INT2: Interrupt Two MOSI F14 MOSI: Master Out Slave In MISO E15 MISO: Master In Slave Out ~CS D15 ~CS: Slave Select (Active Low) SCLK F15 SCLK: Serial Clock ADXL362 Artix 7 Figure 23. Accelerometer interface. 14.1 SPI Interface The ADXL362 acts as a slave device using an SPI communication scheme. The recommended SPI clock frequency ranges from 1 MHz to 5 MHz.
Nexys4 DDR™ FPGA Board Reference Manual 15.1 Pulse Density Modulation (PDM) PDM data connections are becoming more and more popular in portable audio applications, such as cellphones and tablets. With PDM, two channels can be transmitted with only two wires. The frequency of a PDM signal usually falls in the range of 1 MHz to 3 MHz. In a PDM bitstream, a 1 corresponds to a positive pulse and a 0 corresponds to a negative pulse.
Nexys4 DDR™ FPGA Board Reference Manual 15.2 Microphone Digital Interface Timing The clock input of the microphone can range from 1 MHz to 3.3 MHz based on the sampling rate and data precision requirement of the applications. The L/R Select signal must be set to a valid level, depending on which edge of the clock the data bit will be read. A low level on L/RSEL makes data available on the rising edge of the clock, while a high level corresponds to the falling edge of the clock, as shown in Figure 27.
Nexys4 DDR™ FPGA Board Reference Manual Figure 29. Sallen-Key Butterworth Low-Pass 4th Order Filter. The frequency response of SK Butterworth Low-Pass Filter is shown in Figure 30. The AC analysis of the circuit is done using NI Multisim 12.0. 20 MAGNITUDE (DB) 0 -20 -40 -60 -80 -100 1 10 100 1K 10K 100K 1M FREQUENCY (HZ) Stage II Stage I Overall Figure 30. SK Butterworth Low-Pass Filter frequency response. 16.
Nexys4 DDR™ FPGA Board Reference Manual Pulse Width Digital Signal Analog Signal (PWMA) Vdd Gnd Pulse Window = 1 / Pulse Frequency (f) Figure 31. Simple waveform represented as PWM. The PWM signal must be integrated to define an analog voltage. The low-pass filter 3dB frequency should be an order of magnitude lower than the PWM frequency, so that signal energy at the PWM frequency is filtered from the signal.
Nexys4 DDR™ FPGA Board Reference Manual Stressed solder joints can be repaired by reheating and reflowing solder and contaminants can be cleaned with offthe-shelf electronics cleaning products. If a board fails test within the warranty period, it will be replaced at no cost. Contact Digilent for more details. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners.
