300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com Nexys4™ FPGA Board Reference Manual Nexys4 rev. B; Revised November 19, 2013 Overview The Nexys4 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx.
Nexys4™ FPGA Board Reference Manual The Nexys4 is compatible with Xilinx’s new high-performance Vivado ® Design Suite as well as the ISE toolset, which includes ChipScope and EDK. Xilinx offers free “Webpack” versions of these toolsets, so designs can be implemented at no additional cost. 24 23 22 21 20 19 18 17 1 16 2 15 14 3 13 12 4 4 5 11 6 4 4 7 10 8 9 Figure 1.
Nexys4™ FPGA Board Reference Manual A growing collection of board support IP, reference designs, and add-on boards are available on the Digilent website. See the Nexys4 page at www.digilentinc.com for more information. 1 Power Supplies The Nexys4 board can receive power from the Digilent USB-JTAG port (J6) or from an external power supply. Jumper JP3 (near the power jack) determines which source is used. All Nexys4 power supplies can be turned on and off by a single logic-level power switch (SW16).
Nexys4™ FPGA Board Reference Manual Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, and 1.0V supplies from the main power input. Table 2 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs). Supply Circuits Device Current (max/typical) 3.3V FPGA I/O, USB ports, Clocks, RAM I/O, Ethernet, SD slot, Sensors, Flash IC17: ADP2118 3A/0.1 to 1.5A 1.
Nexys4™ FPGA Board Reference Manual Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a new configuration file using the JTAG port. An Artix-7 100T bitstream is typically 30,606,304 bits and can take a long time to transfer.
Nexys4™ FPGA Board Reference Manual Quad-SPI programming can be done using the iMPACT tool included with ISE or the labtools version of Vivado. 2.3 USB Host and Micro SD Programming You can program the FPGA from a pen drive attached to the USB-HID port (J5) or a microSD card inserted into J1 by doing the following: 1. 2. 3. 4. 5. 6. Format the storage device (Pen drive or microSD card) with a FAT32 file system. Place a single .bit configuration file in the root directory of the storage device.
Nexys4™ FPGA Board Reference Manual ADDR(22:0) DATA(15:0) CellRAM SPI Flash Artix-7 See Table H14 R11 T15 T13 T14 OE# WE# CLK ADV# WAIT L18 J13 J15 J14 CE# UB# LB# CRE L13 K17 K18 L14 M14 E9 CS# SDI/DQ0 SDO/DQ1 WP#/DQ2 HLD#/DQ3 SCK SPI Flash Cellular RAM Figure 4.
Nexys4™ FPGA Board Reference Manual Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details. EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII.
Nexys4™ FPGA Board Reference Manual clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Project Navigator or Core Generator tools. 6 USB-UART Bridge (Serial Port) The Nexys4 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that allows you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from www.ftdichip.
Nexys4™ FPGA Board Reference Manual SD MICRO (J1) SD/USB (JP2) 2 HOST (J5) microSD User I/O 7 FPGA Config PS2_CLK PS2_DAT FPGA Config F4 B2 PIC24FJ128 Artix-7 Figure 7. Nexys4 PIC24 Connections 7.1 HID Controller The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores.
Nexys4™ FPGA Board Reference Manual 7.2 Keyboard The keyboard uses open-collector drivers so the keyboard, or an attached host device, can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only ports). PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every 100ms.
Nexys4™ FPGA Board Reference Manual Command Action ED Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns FA after receiving ED, then host sends a byte to set LED status: bit 0 sets Scroll Lock, bit 1 sets Num Lock, and bit 2 sets Caps lock. Bits 3 to 7 are ignored. EE Echo (test). Keyboard returns EE after receiving EE F3 Set scan code repeat rate. Keyboard returns F3 on receiving FA, then host sends second byte to set the repeat rate. FE Resend.
Nexys4™ FPGA Board Reference Manual Command EA F4 F5 F3 Action Set stream mode. The mouse responds with "acknowledge" (0xFA) then resets its movement counters and enters stream mode. Enable data reporting. The mouse responds with "acknowledge" (0xFA) then enables data reporting and resets its movement counters. This command only affects behavior in stream mode. Once issued, mouse movement will automatically generate a data packet. Disable data reporting.
Nexys4™ FPGA Board Reference Manual Figure 11. Nexys4 VGA Interface 8.1 VGA System Timing VGA signal timings are specified, published, copyrighted, and sold by the VESA organization (www.vesa.org). The following VGA system timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode. NOTE: For more precise information, or for information on other VGA frequencies, refer to documentation available at the VESA website.
Nexys4™ FPGA Board Reference Manual Anode (entire screen) Cathode ray tube Deflection coils Grid Electron guns (Red, Blue, Green) Cathode ray R,G,B signals (to guns) VGA cable High voltage deflection grid supply (>20kV) control control gun control Figure 12. Color CRT display Electron beams emanate from “electron guns” which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a “grid.
Nexys4™ FPGA Board Reference Manual pixel 0,0 pixel 0,639 640 pixels per row are displayed during forward beam trace Display Surface pixel 479,0 Retrace - no information displayed during this time pixel 479,639 Stable current ramp - information is displayed during this time Current waveform through horizontal defletion coil Total horizontal time Horizontal display time retrace time time HS "front porch" Horizontal sync signal sets retrace frequency "back porch" Figure 13.
Nexys4™ FPGA Board Reference Manual TS Tfp Tdisp T pw Symbol Parameter TS Sync pulse T disp Display time Tbp Horiz. Sync Vertical Sync Time Clocks Lines Time Clks 16.7ms 416,800 521 32 us 800 15.36ms 384,000 480 25.6 us 640 1,600 2 3.84 us 96 T pw T fp Pulse width 64 us Front porch 320 us 8,000 10 640 ns 16 T bp Back porch 928 us 23,200 29 1.92 us 48 Figure 14.
Nexys4™ FPGA Board Reference Manual Figure 16. General Purpose I/O devices on the Nexys4 The sixteen individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible indicate power-on, FPGA programming status, and USB and Ethernet port status. 9.
Nexys4™ FPGA Board Reference Manual can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in Fig 17. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful. Figure 17.
Nexys4™ FPGA Board Reference Manual continuously illuminated. If the update, or “refresh”, rate is slowed to around 45 hertz, a flicker can be noticed in the display. For each of the four digits to appear bright and continuously illuminated, all eight digits should be driven once every 1 to 16ms, for a refresh frequency of about 1KHz to 60Hz. For example, in a 62.
Nexys4™ FPGA Board Reference Manual signals (pins 5 and 11), and eight logic signals, as shown in Fig 20. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching. Pin assignments for the Pmod I/O connected to the FPGA are shown in Table 6. VCC GND 8 signals Pin 1 Pin 6 Pin 12 Figure 20.
Nexys4™ FPGA Board Reference Manual XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.
Nexys4™ FPGA Board Reference Manual 12.1 I2C Interface The ADT7420 chip acts as a slave device using the industry standard I2C communication scheme. To communicate with ADT7420 chip, the I2C master must specify a slave address (0x4B) and a flag indicating whether the communication is a read (1) or a write (0). Once specifications are made for communication, a data transfer takes place.
Nexys4™ FPGA Board Reference Manual 13 Accelerometer The Nexys4 includes an Analog Device ADXL362 accelerometer. The ADXL362 is a 3-axis MEMS accelerometer that consumes less than 2 μA at a 100 Hz output data rate and 270 nA when in motion triggered wake-up mode. Unlike accelerometers that use power duty cycling to achieve low power consumption, the ADXL362 does not alias input signals by under-sampling; it samples the full bandwidth of the sensor at all data rates.
Nexys4™ FPGA Board Reference Manual 14 Microphone The Nexys4 board includes an omnidirectional MEMS microphone. The microphone uses an Analog Device ADMP421 chip which has a high signal to noise ratio (SNR) of 61dBA and high sensitivity of -26 dBFS. It also has a flat frequency response ranging from 100Hz to 15kHz. The digitized audio is output in the pulse density modulated (PDM) format. The component architecture is shown in Figure 24.
Nexys4™ FPGA Board Reference Manual Sum Integrator Out Flip-flop Output 0.4-0=0.4 0+0.4=0.4 0 0.4-0=0.4 0.4+0.4=0.8 1 0.4-1=-0.6 0.8-0.6=0.2 0 0.4-0=0.4 0.2+0.4=0.6 1 0.4-1=-0.6 0.6-0.6=0 0 0.4-0=0.4 0+0.4=0.4 0 0.4-0=0.4 0.4+0.4=0.8 1 0.4-1=-0.6 0.8-0.6=0.2 0 Table 7. Sigma Delta Modulator with a 0.4Vdd input To keep things simple here, assume that the analog input and digital output have the same voltage range 0~Vdd.
Nexys4™ FPGA Board Reference Manual 83.2ns Counter 1 Counting 128 Samples 53.3ns Clock Data 0.416ns Counter 1 Counting 128 Samples 0 1 ... 0 1 1 ... 0 1 1 ... 0 1 1 ... 0 1 1 41.6ns 128 Samples Counter 2 Counting Figure 28. Sampling PDM with two counters 15 Mono Audio Output th The on-board audio jack (J8) is driven by a Sallen-Key Butterworth Low-pass 4 Order Filter that provides mono audio output. The circuit of the low pass filter is shown in Fig 29.
Nexys4™ FPGA Board Reference Manual 20 MAGNITUDE (DB) 0 -20 -40 -60 -80 -100 1 10 100 1K 10K 100K 1M FREQUENCY (HZ) Stage II Stage I Overall Figure 30. SK Butterworth Low Pass Filter frequency response 15.1 Pulse-Width Modulation A pulse-width modulated (PWM) signal is a chain of pulses at some fixed frequency, with each pulse potentially having a different width.
Nexys4™ FPGA Board Reference Manual Vdd PWMA = 0.1·Vdd PWMA = 0.5·Vdd PWMA = 0.9·Vdd Gnd 10% Duty Cycle 50% Duty Cycle 90% Duty Cycle Figure 32. Representation of a PWM integrator producing an output voltage by integrating the pulse train 16 Built-In Self-Test A demonstration configuration is loaded into the SPI Flash device on the Nexys4 board during manufacturing. The source code and prebuilt bitstream for this design are available for download from the Digilent website.
