Manual

ManualsBrandsDigilent ManualsHardware410-178P-KIT

™

Revision: August 5, 2013

Note: This document applies to REV C of the board.

1300 Henley Court | Pullman, WA 99163

(509) 334 6306 Voice and Fax

Doc: 502-178 page 1 of 22

Overview

The Atlys circuit board is a complete,

ready-to-use digital circuit development

platform based on a Xilinx Spartan-6 LX45

FPGA, speed grade -3. The large FPGA

and on-board collection of high-end

peripherals including Gbit Ethernet, HDMI

Video, 128MByte 16-bit DDR2 memory,

and USB and audio ports make the Atlys

board an ideal host for a wide range of

digital systems, including embedded

processor designs based on Xilinx’s

MicroBlaze. Atlys is compatible with all

Xilinx CAD tools, including ChipScope,

EDK, and the free ISE WebPack™, so

designs can be completed at no extra

cost.

The Spartan-6 LX45 is optimized for high-

performance logic and offers:

 6,822 slices, each containing four 6-

input LUTs and eight flip-flops

 2.1Mbits of fast block RAM

 four clock tiles (eight DCMs & four

PLLs)

 six phase-locked loops

 58 DSP slices

 500MHz+ clock speeds

The Atlys board includes Digilent's newest

Adept USB2 system, which offers device

programming, real-time power supply

monitoring, automated board tests, virtual

I/O, and simplified user-data transfer

facilities.

A comprehensive collection of board

support IP and reference designs, and a

large collection of add-on boards are

available on the Digilent website. See the

Atlys page at www.digilentinc.com for

more information.

DDR2

128MByte

SPI Flash (x4)

16Mbyte

High-Speed

Expansion

USB HID Host

Mouse/Keyboard

Spartan-6

XC6SLX45

CSG324C

Basic I/O

LEDs, Btns, Swts

Pmod Port

Expansion

USB-UART

HDMI IN

HDMI OUT

Clock 100MHz

Adept USB2

Config & data

10/100/1000

Ethernet PHY

AC-97 Audio

Codec

Summary of content (22 pages)

PAGE 1
Atlys™ Board Reference Manual Revision: August 5, 2013 Note: This document applies to REV C of the board. 1300 Henley Court | Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Atlys circuit board is a complete, ready-to-use digital circuit development platform based on a Xilinx Spartan-6 LX45 FPGA, speed grade -3.
PAGE 2
Atlys Reference Manual Features              Xilinx Spartan-6 LX45 FPGA, 324-pin BGA package 128Mbyte DDR2 with 16-bit wide data 10/100/1000 Ethernet PHY on-board USB2 ports for programming and data transfer USB-UART and USB-HID port (for mouse/keyboard) two HDMI video input ports and two HDMI output ports AC-97 Codec with line-in, line-out, mic, and headphone real-time power monitors on all power rails 16Mbyte x4 SPI Flash for configuration and data storage 100MHz CMOS oscillator 48 I/O’s ro
PAGE 3
Atlys Reference Manual Both Digilent and Xilinx freely distribute software that can be used to program the FPGA and the SPI ROM. Programming files are stored within the FPGA in SRAM-based memory cells. This data defines the FPGA’s logic functions and circuit connections, and it remains valid until it is erased by removing power or asserting the PROG_B input, or until it is overwritten by a new configuration file. FPGA configuration files transferred via the JTAG port use the .bin or .
PAGE 4
Atlys Reference Manual Adept’s high-speed USB2 system can be used to program the FPGA and ROM, run automated board tests, monitor the four main board power supplies, add PC-based virtual I/O devices (like buttons, switches, and LEDs) to FPGA designs, and exchange register-based and file-based data with the FPGA. Adept automatically recognizes the Atlys board and presents a graphical interface with tabs for each of these applications.
PAGE 5
Atlys Reference Manual Programming Interface To program the Atlys board using Adept, first set up the board and initialize the software:      plug in and attach the power supply plug in the USB cable to the PC and to the USB port on the board start the Adept software turn ON Atlys' power switch wait for the FPGA to be recognized. Use the browse function to associate the desired .bit file with the FPGA, and click on the Program button.
PAGE 6
Atlys Reference Manual Test Interface The test interface provides an easy way to verify many of the board's hardware circuits and interfaces. These are divided into two major categories: on-board memory (DDR2 and Flash) and peripherals. In both cases, the FPGA is configured with test and PCcommunication circuits, overwriting any FPGA configuration that may have been present. Clicking the Run RAM/Flash Test button will perform a walking ‘1’ test on the DDR2 memory and verify the IDCODE in the SPI Flash.
PAGE 7
Atlys Reference Manual Historical data is available using the Show Graph feature, which shows a graph with current data for all four power supplies for up to ten minutes. Recorded values are also stored in a buffer that can be saved to a file for later analysis. Save Buffer and Clear Buffer are used to save and clear the historical data in the buffer. Register I/O The register I/O tab requires that a corresponding IP block, available in the Parallel Interface reference design (DpimRef.
PAGE 8
Atlys Reference Manual File I/O The File I/O tab can transfer files between the PC and the Atlys FPGA. A number of bytes (specified by the Length value) can be streamed into a specified register address from a file or out of a specified register address into a file. During upload and download, the file start location can be specified in terms of bytes. As with the Register I/O tab, File I/O also requires specific IP to be available in the FPGA.
PAGE 9
Atlys Reference Manual Power Supplies The Atlys board requires an external 5V, 4A or greater power source with a coax center-positive 2.1mm internal-diameter plug (a suitable supply is provided as a part of the Atlys kit). Voltage regulator circuits from Linear Technology create the required 3.3V, 2.5V, 1.8V, 1.0V, and 0.9V supplies from the main 5V supply.
PAGE 10
Atlys Reference Manual I2C Bus To Digilent Adept USB .01Ω LT3501 Power Switch 3.3V 3A Regulator OFF EN PG LTC2481 IC16 ON .01Ω LTC3546 2.5V 1A Regulator Power Jack VU EN PG LTC2481 IC15 Battery Connector .01Ω LT3501 1.8V 3A Regulator J12 EN Power Select Jumper JP13 PG LTC2481 IC16 .01Ω LTC3546 1.2V 3A Regulator EN PG LTC2481 IC15 Load Switch Vswt LTC3413 0.9V DDR Term. Reg.
PAGE 11
Atlys Reference Manual and control signals are delay-matched and impedance-controlled. Address and control signals are terminated through 47-ohm resistors to a 0.9V VTT, and data signals use the On-Die-Termination (ODT) feature of the DDR2 chip. Two well-matched DDR2 clock signal pairs are provided so the DDR can be driven with low-skew clocks from the FPGA. When generating a MIG core for the MIRA part, selecting the “EDE1116AXXX-8E” device will result in the correct timing parameters being set.
PAGE 12
Atlys Reference Manual design on the Digilent website provides an example of driving the Flash memory from an FPGA-based design. A board test/demonstration program is loaded into the SPI Flash during manufacturing. That configuration, also available on the Digilent webpage, can be used to demonstrate and check all of the devices and circuits on the Atlys board. Ethernet PHY The Atlys board includes a Marvell Alaska Tri-mode PHY (the 88E1111) paired with a Halo HFJ111G01E RJ-45 connector.
PAGE 13
Atlys Reference Manual The Atlys Base System Builder (BSB) support package automatically generates a test application for the Ethernet MAC; this can be used as a reference for creating custom designs. ISE designs can use the IP Core Generator wizard to create a tri-mode Ethernet MAC controller IP core.
PAGE 14
Atlys Reference Manual HDMI Type A Connectors HDMI Type D Pin/Signal J1: IN J2: Out J3: IN 1: D2+ 2: D2_S 3: D24: D1+ 5: D1_S 6: D17: D0+ 8: D0_S 9: D010: Clk+ 11: Clk_S 12: Clk13: CEC 14: RES 15: SCL 16: SDA 17: Gnd 18: 5V 19: HPD B12 B8 J16 GND GND GND A12 B11 A8 C7 J18 L17 GND GND GND A11 G9 A7 D8 L18 K17 GND GND GND F9 D11 C8 B6 K18 H17 GND GND GND C11 A6 H18 NC 0K to Gnd NC NC NC NC C13 A13 D9 C9 M16 M18 GND JP4* GND 5V GND 1K to 5V NC *jumper can discon
PAGE 15
Atlys Reference Manual (playback) sampling rates can be different. The microphone jack is mono, all other jacks are stereo. The headphone jack is driven by the audio codec's internal 50mW amplifier. The table below summarizes the audio signals. The LM4550 audio codec is compliant to the AC ‘97 v2.1 (Intel) standard and is connected as a Primary Codec (ID1 = 0, ID0 = 0). The table below shows the AC ‘97 codec control and data signals. All signals are LVCMOS33.
PAGE 16
Atlys Reference Manual DCMs provide the four phases of the input frequency (0º, 90º, 180º, and 270º), a divided clock that can be the input clock divided by any integer from 2 to 16 or 1.5, 2.5, 3.5... 7.5, and two antiphase clock outputs that can be multiplied by any integer from 2 to 32 and simultaneously divided by any integer from 1 to 32. PLLs use VCOs that can be programmed to generate frequencies in the 400MHz to 1080MHz range by setting three sets of programmable dividers during FPAG configuration.
PAGE 17
Atlys Reference Manual To access the USB host controller, EDK designs can use the standard PS/2 core. Reference designs posted on the Digilent website show an example for reading characters from a USB keyboard connected to the USB host interface.
PAGE 18
Atlys Reference Manual sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30KHz) when the data is sent, and data is valid on the falling edge of the clock. Scan codes for most PS/2 keys are shown in the figure below.
PAGE 19
Atlys Reference Manual Basic I/O The Atlys board includes six pushbuttons, eight slide switches, and eight LEDs for basic digital input and output. One pushbutton has a red plunger and is labeled "reset" on the PCB silkscreen – this button is no different than the other five, but it can be used as a reset input to processor systems. The buttons and slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits.
PAGE 20
Atlys Reference Manual Expansion Connectors The Atlys board has a 68-pin VHDC connector for high-speed/parallel I/O, and an 8-pin Pmod connector for lower speed and lower pin-count I/O. The VHDC connector includes 40 data signals (routed as 20 impedance-controlled matched pairs), 20 grounds (one per pair), and eight power signals. This connector, commonly used for SCSI-3 applications, can accommodate data rates of several hundred megahertz on every pin.
PAGE 21
Atlys Reference Manual VHDC Connector Pinout IO1-P: IO2-P: IO3-P: IO4-P: IO5-P: IO6-P: IO7-P: IO8-P: IO9-P: IO10-P: U16 U15 U13 M11 R11 T12 N10 M10 U11 R10 IO1-N: IO2-N: IO3-N: IO4-N: IO5-N: IO6-N: IO7-N: IO8-N: IO9-N: IO10-N: V16 V15 V13 N11 T11 V12 P11 N9 V11 T10 IO11-P: IO12-P: IO13-P: IO14-P: IO15-P: IO16-P: IO17-P: IO18-P: IO19-P: IO20-P: U10 R8 M8 U8 U7 N7 T6 R7 N6 U5 IO11-N: IO12-N: IO13-N: IO14-N: IO15-N: IO16-N: IO17-N: IO18-N: IO19-N: IO20-N: V10 T8 N8 V8 V7 P8 V6 T7 P7 V5 The Pmod connec
PAGE 22
Atlys Reference Manual Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod and VHDC expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, cameras and other functions. See www.digilentinc.com for more information. Built-In Self Test A demonstration configuration is loaded into the SPI Flash ROM on the Atlys board during manufacturing.