Datasheet

PmodACL™ Reference Manual
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Page 2 of 3
Read/~Write
Multi-byte
6-bit Threshold Activity Address
0
0
1
0
0
1
0
0
8 bits of Threshold Activity data (62.5 mg/LSB scale)
0
0
0
0
0
1
0
0
Read/~Write
Multi-byte
6-bit Activity/Inactivity Control Address
0
0
1
0
0
1
1
1
Activity/Inactivity Control Settings
ACT ac/dc
ACT X
ACT Y
ACT Z
INACT ac/dc
INACT X
INACT Y
INACT Z
0
1
1
0
0
0
0
0
Read/~Write
Multi-byte
6-bit Interrupt Enable Address
0
0
1
0
1
1
1
0
8 bits of Which Interrupt Sources Are Enabled
Data Ready
Single Tap
Double Tap
Activity
Inactivity
Free Fall
Watermark
Overrun
0
0
0
1
0
0
0
0
Table 1. Data stream setting the threshold activity through SPI
Once an interrupt has been generated, users may read the data registers (0x32 - 0x37) for the 10 bits of two's
complement data in the X, Y, and Z axes, respectively. The data in the two registers for each axis is right-justified
with sign extensions as the leading 6 bits. Reading the Interrupt source register (0x30) clears the activity interrupt
bit D4.
Users may also follow the given example code functions and demonstration to start collecting accelerometer data.
2.1 Pinout Description Table
Pin
Signal
Description
1
~CS
Chip Select
2
MOSI
Master-out-slave-in
3
MISO
Master-in-slave-out
4
SCK
Serial Clock
5
GND
Power Supply Ground
6
VCC
Power Supply (3.3V)
7
INT2
Interrupt 2
8
INT1
Interrupt 1
9
NC
Not Connected
10
NC
Not Connected
11
GND
Power Supply Ground
12
VCC
Power Supply (3.3V)
Any external power applied to the PmodACL must be within 2.0V and 3.6V; however, it is strongly recommended
that the Pmod is operated at 3.3V.
Pin
Signal
Description
1, 5
SCL
Serial Clock
2, 6
SDA
Serial Data
3, 7
GND
Power Supply Ground
4, 8
VCC
Positive Power Supply
Table 2. Pmod header J1.
Table 3. Pmod header J2.