Datasheet

JTAG -SMT2™ Programming Module for Xilinx® FPGAs
Copyright Digilent, Inc. All rights reserved.
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Page 11 of 12
8 AC Operating Characteristics
The JTAG-SMT2’s JTAG signals operate according to the timing diagram in Fig. 12. The SMT2 supports JTAG/TCK
frequencies from 30 MHz to 8 KHz at integer divisions of 30 MHz from 1 to 3750. Common frequencies include 30
MHz, 15 MHz, 10 Mhz, 7.5 MHz, and 6 MHz (see Table 2). The JTAG/TCK operating frequency can be set within the
Xilinx Tools. Note: Please refer to Xilinx’s iMPACT documentation for more information.
TDI
TCK
TDO
T
CKH
T
CKL
T
CK
T
CD_TDI
T
HD
T
SETUP
TMS
T
CD_TMS
9 Mounting to Host PCBs
The JTAG-SMT2 module has a moisture sensitivity level (MSL) of 6. Prior to reflow, the JTAG-SMT2 module must be
dried by baking it at 125° C for 17 hours. Once this process has been completed, the module has a MSL of 3 and is
suitable for reflow for up to 168 hours without additional drying.
The factory finishes the JTAG-SMT2 signal pads with the ENIG process using 2u” gold over 150u” electroless nickel.
This makes the SMT2 compatible with most mounting and reflow processes (see Fig. 13). The binding force of the
solder is sufficient to hold the SMT2 firmly in place so mounting should require no additional adhesives.
Symbol
Parameter
Min
Max
T
CK
T
CK
period
30ns
125µs
T
CKH
, T
CKL
T
CLK
pulse width
15ns
62.5µs
T
CD_TMS
T
CLK
to TMS
-0.5ns
12.35ns
T
CD_TDI
T
CLK
to TDI
-0.5ns
8.15ns
T
SETUP
TDO Setup time
15.8ns
T
HD
TDO Hold time
0ns
Figure 12. Timing diagram.
Figure 12. Timing diagram.
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Note
Table 2. JTAG signal timing.
Note: these parameters are specified for Vref = 3.3V.