User's Manual

4-14 72000 Development Kit User’s Guide MOTOROLA
Preliminary
Hardware
4.4.4 Memory
The MC72000 has embedded memory of 256 Kbytes of ROM and 64 K of RAM. The file system and
application can be uploaded from a host system, or a low-cost serial EEPROM (four-wire connection). For
more information on the contents and structure of the MC72000 memory, please refer to the Bluetooth
Platform Solution Embedded System User’s Guide. This is accessible from the document overview on the
Development Kit CD.
4.4.5 UART Interface
The UART interface is embedded in the MC72000. However, an external level converter is needed. For
this purpose, the MAX3237 1.0 Mbit level converter is used. The level converter is connected to the
MC72000 and a female 9-pin D-sub. The connection between the level converter and the MC72000 is
passed through a jumper block in order to aid debugging, and, if ever needed, to use a different type of
level converter.
4.4.6 CODEC Interface
The audio interface consists of the Motorola MC145483 CODEC, a 4-pin header and a 4/4p amp
connector. Sampling rate is configured at 7.8125 kHz.
4.4.6.1 Codec Setup and Configuration
In the current (Motorola CODEC) configuration for the 72000 Development Kit, the CODEC can only be
configured as a slave, which is done by the application at startup. Therefore, the MC72000 IC will be
configured as the SSI master, meaning that the MC72000 IC generates all SSI control signals. In practice,
the CODEC bit clock is tied electrically to the master clock.
There are certain constraints on the available clock frequencies; specifically, the frequency can only be
integer factors of the baseband’s master clock, which is 24 MHz. The Motorola CODEC expects a 2.048
MHz master clock, but due to these limitations, none of the available integral frequencies fit the CODEC
exactly. Therefore, a slight mismatch in the order of two per cent exists. To be exact, the CODEC expects
a 2.048 MHz master clock, but gets 2.000 MHz.
The frame sync generated by the MC72000 IC can only by an integer factor of the master clock (bit clock),
and is selected as 1/256th, resulting in:
• Frame sync: 2000 kHz / 256 = 7.8125 kHz
This slight mismatch does not cause any audio degredation. Interpolation copes with the synchronization
seamlessly. The degradation of the frequency characteristic of the system from runnning on a slightly
lower sample frequency is not significant. (The pass-band upper frequency is 3.9 kHz instead of 4.0 kHz).
Figure 4-1. SSI Signals from Baseband to CODEC
STXD
SRXD
STCK
STFS
Motorola CODEC