User Manual

Functional Description
MOTOROLA MC13192 Product Preview 9
5.2 Serial Peripheral Interface (SPI)
Control of the MC13192 and data transfers are accomplished by means of a 4-wire Serial Peripheral
Interface (SPI). This section details the operation of the SPI.
5.2.1 General
The MC13192 operates as a slave device only. Data to be written into the IC is presented on the Master
Out/Slave In (MOSI) pin of the device, while data read from the device is presented to the master device
on the Master In/Slave Out (MISO) pin. Synchronization of the data is accomplished by the return-to-zero
Serial Clock (SPICLK) input and is framed by the Chip Enable (CE
) pin. Data on MOSI is always clocked
into the IC on the leading edge of SPICLK and data is clocked out of the IC at MISO on the falling edge of
SPICLK. The master device should transfer MISO data to its internal registers on the trailing edge of
SPICLK. A typical interconnection to a microprocessor is shown in Figure 4.
Figure 4. SPI Interface
MISO is an active output and as such, does not enter a high impedance state at any time regardless of the
state of CE
.
Although the SPI is fully static, internal memory, timer and interrupt arbiters require an internal clock,
CLK
core
, derived from the crystal reference oscillator, to communicate from the SPI registers to internal
registers and memory.
Figure 5 and Table 7 show the SPI timing diagram and timing specifications.
Figure 5. SPI Parametric Timing Diagram.
Shift Register
Baud Rate
Generator
Shift Register
Chip Enable (CE)
RxD
MISO
TxD MOSI
Sclk SPICLK
MCU MC13192
CE
MISO
SPICLK
CE
t
PER
t
CLKH
t
CLKL
t
CE_SU
MOSI Addr 1R/W
Read 0
t
SU
t
H
t
SU
t
H
t
P1
t
P1
Write 0
Read 1
t
CE_H
t
SU
t
H
Fr
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Freescale Semiconductor, Inc.
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