User Manual

4 MC13192 Product Preview MOTOROLA
Data Transfer Modes
In streaming mode, the data is fed to the MC13192 on a word by word basis with an interrupt serving as a
notification that the MC13192 is ready for more data. This continues until the whole packet is transmitted.
Figure 1. MC13192 Simplified Block Diagram
Figure 2. System Level Block Diagram
Phase Shift Modulator
RST
GPIO1
GPIO2
GPIO3
GPIO4
Crystal2
Crystal1
RFIN-
RFIN+
PAO+
PAO-
MOSI
MISO
SPICLK
RXTXEN
CE
ATTN
GPIO5
GPIO6
GPIO7
Receive
Packet RAM
Transmit
Packet RAM 1
Transmit RAM
Arbiter
Receive RAM
Arbiter
PA
VCO
Crystal
Oscillator
Symbol
Generation
FCS
Generation
Header
Generation
MUX
Sequence
Manager
(Control Logic)
VDDLO2
÷4
256MHz
2.45GHz
LNA
1st IF Mixer
IF = 65 MHz
2nd IF Mixer
IF = 1 MHz
PMA
Decimation
Filter
Matched
Filter
Baseband
Mixer
DCD
Correlator
Symbol
Synch & Det
CCA
Packet
Processor
IRQ
Arbiter
24 Bit Event Timer
IRQ
16MHz
AGC
Analog
Regulator
VBATT
Digital
Regulator L
Digital
Regulator H
Power-Up
Control
Logic
Crystal
Regulator
VCO
Regulator
VDDINT
Programmable
Prescaler
CLKO
4 Programmable
Timer Comparators
Synthesizer
VDDD
VDDVCO
SERIAL
PERIPHERAL
INTERFACE
(SPI)
VDDA
VDDLO1
Transmit
Packet RAM 2
Analog Receiver
MC13192
Frequency
Generation
Analog
Transmitter
Voltage
Regulators
Power Up
Management
Control
Logic
Buffer RAM
Digital Transceiver
SPI
and GPIO
Microcontroller
SPI
Rom (Flash)
RAM
CPU A/D
Timer
Application
IRQ Arbiter
RAM Arbiter
Timer
Network
MAC
PHY Driver
Fr
eescale S
emiconduct
or
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Freescale Semiconductor, Inc.
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