User Manual

Block Diagrams
MOTOROLA MC13192 Product Preview 3
2 Block Diagrams
Figure 1 shows a simplified block diagram of the MC13192. The MC13192 is an IEEE 802.15.4
transceiver that provides most of the functions required in the Physical Layer (PHY) specification.
Figure 2 shows the basic system block diagram for the MC13192 in an application. Interface with the IC is
accomplished through a 4-wire Serial Peripheral Interface (SPI). The Medium Access Control (MAC),
drivers, and Network and Application software as required reside on the host processor. The host can be
anything from a simple 8-bit device up to a sophisticated 32-bit processor depending on application
requirements.
3 Data Transfer Modes
The MC13192 has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word by word
When using the Motorola 802.15.4 MAC, only the streaming mode can be used. For proprietary
applications, packet mode is used to conserve MCU resources.
3.1 Packet Structure
Figure 3 shows the packet structure of the MC13192. Payloads of up to 125 bytes are supported. The
MC13192 adds a four byte preamble, a one byte start of frame delimiter (SFD), and a one byte frame
length indicator before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of
the data.
3.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down conversion stages. A Clear Channel Assessment (CCA) can be performed based on the
baseband energy integrated over a specific time interval. The digital back end performs Differential Chip
Detection (DCD), the correlator “de spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK
(O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and frame length are parsed and used. A two-byte FCS is calculated and compared to
the FCS value appended to the transmitted data, generating a Cyclical Redundancy Check (CRC) result.
Link Quality is measured over a 64 µs period after the packet preamble and stored in ROM.
If the MC13192 is in packet mode, the data is processed as an entire packet. The MCU is notified that an
entire packet has been received via an interrupt.
If the MC13192 is in streaming mode, the MCU is notified by an interrupt on a word by word basis.
3.3 Transmit Path Description
The transmit path is the exact reverse of the receive path. The data stored in RAM is retrieved or clocked in
via the SPI, formed into packets per the 802.15.4 PHY, spread, and then up converted to the transmit
frequency.
If the MC13192 is in packet mode, data is processed as an entire packet. The data is loaded into the TX
buffer. The MCU then requests that the MC13192 transmit the data. The MCU is notified that the whole
packet has successfully been transmitted via an interrupt.
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