User`s manual

When IRQ and address selection are acceptable, the adapter memory
is tested. ‘Ihe test does write/verify at every location with word
accesses only. Each 16K memory window is selected and tested
independently. Address and data buses are tested separately.
The program then runs a window uniqueness test. A different, single
word is written to each of the eight 16K windows; then the test reads
each window to verify that the windows are indeed unique.
When prompted, install the single channel loopback connector onto
line 1 (the lower connector for Micro Channel). The wiring diagram
for the loopback connector is in the appendix pertaining to your
version of SYNC/570 or SYIW57Oi. The diagnostics program tests the
control and data lines. The control line loopback tests RI’S to CTS,
and DTR to DSR to DCD. The data loopback test is the default single
channel chained-block DhL4 transfer mode test. When the line 1 tests
are complete, install the loopback connector on line 2 (the upper
connector for Micro Channel). The tests will be repeated for line 2.
The diagnostics program also tests the ability of the card to generate
interrupts by way of internal data loopbacks. It tests all found ports.
For example, a 4 port board will prompt you to move the loopback
connector when performing the external data and control signal tests.
The internal and external tests are run at the maximum supported bit
rates for their respective interfaces. On the internal tests, all available
channels are run simultaneously at the maximum bit rate to help
resolve arbitration and memory bandwidth issues.
20 Chapter Eight: Using the Diagnostics Disk