International Computer Hardware User Manual

iv
Chapter 3: Working with the CPU ......................................................................47
About the processor....................................................................48
Instruction sets.......................................................................... 49
ARM instruction set.............................................................. 50
Thumb instruction set...........................................................50
Java instruction set ............................................................. 50
System control processor (CP15) registers..........................................51
ARM926EJ-S system addresses .................................................51
Accessing CP15 registers........................................................52
Terms and abbreviations ....................................................... 52
Register summary................................................................ 53
R0: ID code and cache type status registers.................................55
R1: Control register .............................................................58
R2: Translation Table Base register........................................... 61
R3: Domain Access Control register........................................... 61
R4 register ........................................................................62
R5: Fault Status registers.......................................................62
R6: Fault Address register......................................................64
R7: Cache Operations register................................................. 64
R8:TLB Operations register.....................................................68
R9: Cache Lockdown register .................................................. 69
R10: TLB Lockdown register.................................................... 73
R11 and R12 registers ........................................................... 74
R13: Process ID register......................................................... 75
R14 register.......................................................................77
R15: Test and debug register ..................................................77
Jazelle (Java) ........................................................................... 77
DSP........................................................................................78
Memory Management Unit (MMU) ....................................................78
MMU Features .................................................................... 78
Address translation.............................................................. 81
MMU faults and CPU aborts..................................................... 95
Domain access control .......................................................... 98
Fault checking sequence .......................................................99
External aborts..................................................................102
Enabling the MMU...............................................................103
Disabling the MMU ..............................................................104