Specifications

Digi m10 Hardware Reference v 1.20
Digi International, Inc. © 2013
Page 15 of 38
goes low only after the host controller has cleared the outbound (OB) queue. The Digi m10's
timing diagram for DA is shown in
Figure 6.
Table 6: DA Pin
Pin Name Description
10 DA Data Available
Figure 6: Timing Diagram for Data Available
2.6 RTS/CTS Implementation
Hardware flow control is disabled by default. When it is enabled, hardware flow control is
implemented using RTS (Request to Send ) and (Clear To Send) signals. RTS serves as an input
to the Digi m10 and is controlled by DTE. Alternatively, CTS is an input to DTE and is controlled
by the Digi m10. The RTS line is level sensitive and assertion is 0V while de-assertion is 3.3V.
Pin Name Description
13 RTS 3.3V UART Interface. Host controller to Digi m10
14 CTS 3.3V UART Interface. Digi m10 to Host controller
2.7 SA (Satellite Available)
The Satellite Available is an active high signal. It is normally low and is set to high whenever the
Digi m10 is receiving on valid downlink channel and has valid downlink/uplink channel information
packets. The Digi m10's timing diagram for SA is shown in Figure 7
.
Table 7: SA Pin
Pin Name Description
9 SA Satellite Available