User`s manual

Rabbit 4000 Designer’s Handbook rabbit.com 15

3.3 Basic Memory Design

Normally /CS0 and /OE0 and /WE0 should be connected to a flash memory that holds the startup code that

executes at address zero. When the processor exits reset with (SMODE1, SMODE0) set to (0,0), it will

attempt to start executing instructions at the start of the memory connected to /CS0, /OE0, and /WE0.

For Dynamic C to work out of the box, the basic RAM memory must be connected to /CS1, /OE1, and

/WE1.

/CS1 has a special property that makes it the preferred chip select for battery-backed RAM. The BIOS

defined macro, CS1_ALWAYS_ON, may be redefined in the BIOS to 1 which will set a bit in the MMIDR

tered when the chip select line is passed through a device that is used to place the chip in standby by rais-

ing /CS1 when the power is switched over to battery backup. The battery switchover device typically has a

propagation delay that may be 20 ns or more. This is enough to require the insertion of wait states for

RAM access in some cases. By forcing /CS1 low, the propagation delay is not a factor because the RAM

will always be selected and will be controlled by /OE1 and /WE1. If this is done, the RAM will consume

more power while not battery-backed than it would if it were run with dynamic chip select and a wait state.

If this special feature is used to speed up access time for battery-backed RAM then no other memory chips

should be connected to OE1 and WE1.

Table 3-1 Typical Interface between the Rabbit 4000 and Memory

Primary Flash SRAM Secondary Flash

/CS0, /OE0 and /WE0 /CS1, /OE1 and /WE1 /CS2, /OE0 and /WE0