User`s manual

Rabbit 4000 Designer’s Handbook rabbit.com 11
2.2 ESD Design Guidelines
The following guidelines are recommended for designs incorporating a Rabbit 4000 processor with electro-
static discharge (ESD) sensitivity on VBAT. These guidelines are good recommendations for all Rabbit
processors.
1. The 1.8 V supply for VBAT should be provided by a regulator with at least 2 kV ESD protection
(human body model).
2. The 3.3 V supply should have smaller 0.1 µF, 0.01 µF, and 2.2 nF bypass capacitors throughout the lay-
out. In addition, the 3.3 V supply should have a large value bulk capacitor (10 µF).
The power going to VBAT should also be protected by a diode and two resistors. See a schematic for a
RabbitCore
®
module based on the Rabbit 4000 for more details.
2.3 Operating Voltages
The operating voltage in Rabbit 4000 based systems will usually be 1.8 V ±10% for the processor core and
3.3 V ±10% for the I/O. The I/O ring can also be run at 1.8 V ±10%.
The maximum computation per watt is obtained in the range of 3.0 V to 3.6 V. The highest clock speed
requires 3.3 V. The maximum clock speed with a 3.3 V supply is 54 MHz (26.7264 x 2), but it will usually
be convenient to use a 14.7456 MHz crystal, doubling the frequency to 29.4912 MHz. Good computa-
tional performance, but not the absolute maximum, can be implemented for a 3.3 V system by using an
11.0592 crystal and doubling the frequency to 22.1184 MHz. Such a system will operate with 70 ns memo-
ries. A 29.4912 MHz system will require memories with 55 ns access time. A table of timing specification
is in the Rabbit 4000 Microprocessor User’s Manual.
2.4 Power Consumption
Various mechanisms contribute to the current consumption of the Rabbit 4000 processor while it is operat-
ing, including current that is proportional to the voltage alone (leakage current) and dependent on both
voltage and frequency (switching and crossover current).
Table 2-1 shows typical current draw as a function of the main clock frequency. The values shown do not
include any current consumed by external oscillators or memory. It is assumed that approximately 30 pF is
connected to each address line.
NOTE: VDDCORE = 1.8 V ± 10%, VDDIO = 3.3 V ± 10%, TA = -40°C to 85°C
Table 2-1 Preliminary Current vs. Clock Frequency
Frequency (MHz) I_{core} (mA) I_{IO} (mA) I_{Total} (mA)
7.3728 4 10 14
14.7456 6 11 17
29.4912 10 12 22
58.9824 18 15 33