User manual

Triggers
R&S
®
RTO
74User Manual 1316.0827.02 ─ 06
Setup time
Sets the minimum time before the clock edge while the data signal must stay steady
above or below the data level.
The setup time can be negative. In this case, the hold time is always positive. If you set
a negative setup time, the hold time is adjusted by the instrument.
SCPI command:
TRIGger<m>:DATatoclock:STIMe on page 474
Hold time
Sets the minimum time after the clock edge while the data signal must stay steady above
or below the data level.
The hold time can be negative. In this case, the setup time is always positive. If you set
a negative hold time, the setup time is adjusted by the instrument.
SCPI command:
TRIGger<m>:DATatoclock:HTIMe on page 474
3.3.1.11 Pattern
The pattern trigger is a logic trigger. It provides logical combinations of the input channels
and supports you in verifying the operation of digital logic.
The setup of the pattern trigger is very similar to trigger qualification. In addition to the
pattern and the trigger levels, you can define a timing condition. The complete settings
for the pattern trigger are provided in the "Qualification" tab.
For details on pattern definition, see "Pattern" on page 77.
Trigger Levels
Defines the trigger levels for all input channels. For qualification and pattern trigger, the
trigger level is a decision threshold: If the signal value is higher than the trigger level, the
signal state is high (1 or true for the boolean logic). Otherwise, the signal state is con-
sidered low (0 or false) if the signal value is below the trigger level.
You can set the trigger levels for all channels to the same value, see "Couple levels
(Trigger level and hysteresis coupling)" on page 73.
State timing
"State timing" adds additional time limitation to the state pattern. You find this setting in
the "Qualification" tab.
"Off"
No time limitation. The event occurs if the pattern condition is fulfilled.
Reference for Triggers