User manual

Mixed Signal Option (MSO, R&S RTO-B1)
R&S
®
RTO
338User Manual 1316.0827.02 ─ 06
The hold time can be negative. In this case, the hold time ends before the clock edge,
and the setup interval ends when the hold interval starts. Thus, the setup time is always
positive. If you change the negative hold time, the setup time is adjusted by the instru-
ment.
SCPI command:
TRIGger<m>:PARallel:DATatoclock:HTIMe on page 748
11.3.4.6 State
The state trigger detects the logical state of several logically combined digital channels
at a given clock edge. The trigger source is a logical combination of digital channels or a
parallel bus. The trigger occurs at the clock edge at which the state condition is true.
Fig. 11-6: State trigger settings for trigger source = parallel bus
Clock source
Selects the digital channel of the clock signal.
SCPI command:
TRIGger<m>:PARallel:DATatoclock:CSOurce[:VALue] on page 744
TRIGger<m>:PARallel:STATe:CSOurce:VALue on page 744
TRIGger<m>:PARallel:SPATtern:CSOurce[:VALue] on page 744
Clock edge
Sets the edge of the clock signal. The crossing of the clock edge and the logical threshold
defines the time at which the logical states and the bus value are analyzed.
SCPI command:
TRIGger<m>:PARallel:STATe:CSOurce:EDGE on page 749
Channel states
For each digital channel that is used in the bus, set the required state: 1, 0, or X (don't
care).
SCPI command:
TRIGger<m>:PARallel:STATe:BIT<n> on page 749
Reference for MSO