User manual

Protocol Analysis
R&S
®
RTO
271User Manual 1316.0827.02 ─ 06
For details, see chapter 10.3.3.2, "SPI Trigger", on page 273
10.3.3 Reference for SPI
10.3.3.1 SPI Configuration
Make sure that the tab of the correct serial bus is selected on the left side.
See also: chapter 10.1.1, "Configuration - General Settings", on page 251.
SCLK
Defines the settings for the clock line.
SCLK source ← SCLK
Sets the input channel of the clock line. Waveform 1 of channel signals, math waveforms,
and reference waveforms can be used for decoding. For triggering on a serial bus, a
channel signal is required.
SCPI command:
BUS<m>:SPI:SCLK:SOURce on page 664
Polarity ← SCLK
Two settings define the clock mode: the clock polarity and the clock phase. Together,
they determine the edges of the clock signal on which the data are driven and sampled.
A master/slave pair must use the same parameter pair values to communicate.
The clock polarity is "Idle low" (idle = 0) or "Idle high" (idle = 1).
The clock phase defines the slope. It selects if data is stored with the rising or falling slope
of the clock. The slope marks the begin of a new bit.
SPI Bus