User's Manual

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR
2-6
5 CLOCK MANAGEMENT
5.1 CLOCK GENERATION OVERVIEW
Figure 2-3 shows the block diagram of the clock generation module. The main clock source comes from an
external crystal (XTI) or external clock (EXTCLK). EPLL’s input clock is one of the XTI or EXTCLK. Clock selection
can be done by configuring MUX selection signal. When both XTI and EXTCLK are running, GFM(Glitch Free
Mux)’s output can be configured easily without generating glitch. But if you change or select EPLL input clock
when either XTI or EXTCLK is running, disabled clock should be have logic LOW.
XTI clock source can be reference of PLL after oscillated at PAD. User can configure stabilization time by setting
OSCSET register and ON/OFF when power-down mode by setting PWRCFG register. The clock generator
consists of two PLLs (Phase-Locked-Loop) which generate the high-frequency clock signals required in S3C2450.
MPLL
ExtClk Div
XTI
EXTCLK
OM[0]
ARMCLK
HCLK
PCLK
DDRCLK
SYSCLK
EPLL
XTI
EXTCLK
ECLK
USBHOST
CAMCLK
I2SCLK
UARTCLK
LCDCLK
OM[0]&
CLKSRC
Clock
Divider &
Mux
Figure 2-3. Clock Generator Block Diagram
5.2 CLOCK SOURCE SELECTION
Table 2
-2 and 2-3 show the relationship between the combination of mode control pins OM[0] and the selection of
source clock for S3C2450.
Table 2-2. Clock source selection for the main PLL and clock generation logic
OM[0]
MPLL Reference Clock
(Main clock source)
0 XTI
1 EXTCLK