User's Manual

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR
2-4
POWER
nRESET
EXTCLK
or XTIpll
VCO
output
SYSCLK
PLL is configured by S/W first time
Lock time
VCO is adapte to new clock frequency
.
The logic is operarted by
EXTCLK or XTIpll
SYSCLK is FOUT
Clock
disable
Figure 2-2. Power-On Reset Sequence
4.3 WATCHDOG RESET
Watchdo
g reset is invoked when software fails to prevent the watchdog timer from timing out.
During the watchdog reset, the following actions occur :
• All units(except some blocks listed in table 2-1 ) go into their pre-defined reset state.
• All pins get their reset state, and BATT_FLT pin is ignored.
• The nRSTOUT pin is asserted during watchdog reset.
Watchdog reset can be activated in normal and idle mode because watchdog timer can expire with clock.
Watchdog reset is invoked when watchdog timer and reset are enabled (WTCON[5] = 1, WTCON[0]=1) and
watchdog timer is expired. Watchdog reset is invoked then, the following sequence occurs. :
1. Watchdog reset source asserts.
2. Internal reset signals and nRSTOUT are asserted and reset counter is activated.
3. Reset counter is expired then, internal reset signals and nRSTOUT are deasserted.