User's Manual

S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER
2-1
2 SYSTEM CONTROLLER
1 OVERVIEW
The system controller consists of three parts; reset control, system clock control, and system power-management
control. The system clock control logic in S3C2450 can generate the required system clock signals which are the
inputs of ARM926EJ, several AHB blocks, and APB blocks. There are two PLLs in S3C2450 to generate internal
clocks. One is for general functional blocks, which include ARM, AHB, and APB. The other is for the special
functional clocks which are the USB, I2S and camera interface clock. Software program control the operating
frequency of the PLLs, internal clock sources and enabled or disabled the clocks to reduce the power
consumption.
S3C2450 has various power-down modes to keep optimal power consumption for a given task. The power-down
modes consists of four modes; NORMAL mode, IDLE mode, STOP mode, and SLEEP mode. In NORMAL mode,
the input clock of each block is enabled or disabled according to the software to eliminate the power consumption
of unused blocks for a certain application. For example, if an UART is not needed, the software can disable the
input clock independently. The major power dissipation of S3C2450 is due to ARM core, since the operating
speed is relative higher than that of the other blocks. Typically, the operating frequency of the ARM core is
533MHz, while the AHB blocks and the APB blocks operate on 133MHz and 66MHz, respectively. Thus, the
power control of the ARM core is major issue to reduce the overall power dissipation in S3C2450, and IDLE mode
is supported for this purpose. In IDLE mode, the ARM core is not operated until the external interrupts or internal
interrupts. The STOP mode freezes all clocks to all peripherals as well as the ARM core by disabling PLLs. The
power consumption is only due to the leakage current and the minimized alive block in S3C2450. SLEEP mode is
intended to disconnect the internal power. So, the power consumption due to the ARM core and the internal logic
except the wake-up logic will be nearly zero in the SLEEP mode. In order to use the SLEEP mode two
indenpendent power sources are required. One of the two power soruces supplies the power for the wake-up
logic. The other one supplies the normal functional blocks including the ARM core. It should be controlled in order
to turn ON/OFF with a special pin in S3C2450. The detailed description of the power-saving modes such as the
entering sequence to the specific power-down mode or the wake-up sequence from a power-down mode is given
in the following Power Management section.
2 FEATURE
• Include two on-chip PLLs called main PLL(MPLL), extra PLL(EPLL)
• MPLL generates the system reference clock
• EPLL generates the clocks for the special functional blocks
• Independent clock ON/OFF control to reduce power consumption
• Support three power-down modes, IDLE, STOP, and SLEEP, to optimize the power dissipation
• Wake-up by one of external Interrupt, RTC alarm, Tick interrupt and BATT_FLT.(Stop and Sleep mode)
• Control internal bus arbitration priority