User's Manual

ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR
29-26
Table 29-12. DMA Controller Module Signal Timing Constants
(VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = -40 to 85°C, VDD_OP2 = 3.3V ± 0.3V)
Parameter Symbol Min Typ Max Unit
eXternal Request Setup
t
XRS
6.4/6.4 - 9.9/9.9 ns
aCcess to Ack Delay when Low transition
t
CADL
3.1/2.8 7.8/7.1 ns
aCcess to Ack Delay when High transition
t
CADH
2.8/2.5 7.8/6.9 ns
eXternal Request Delay
t
XAD
2 - - HCLK
Table 29-13. TFT LCD Controller Module Signal Timing Constants
(VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = -40 to 85°C, VDD_LCD = 3.3V ± 0.3V)
Parameter Symbol Min Typ Max Units
VCLK pulse width Tvclk 18 200 - ns
VCLK pulse width high Tvclkh 0.3 - -
Pvclk
(note1)
VCLK pulse width low Tvclkl 0.3 - - Pvclk
Vertical sync pulse width Tvspw VSPW + 1 - -
Phclk
(note2
)
Vertical back porch delay Tvbpd VBPD+1 - - Phclk
Vertical front porch delay Tvfpd VFPD+1 - - Phclk
Hsync setup to VCLK falling edge Tl2csetup 0.3 - - Pvclk
VDEN set up to VCLK falling edge Tde2csetup 0.3 - - Pvclk
VDEN hold from VCLK falling edge Tde2chold 0.3 - - Pvclk
VD setup to VCLK falling edge Tvd2csetup 0.3 - - Pvclk
VD hold from VCLK falling edge Tvd2chold 0.3 - - Pvclk
VSYNC setup to HSYNC falling edge Tf2hsetup HSPW + 1 - - Pvclk
VSYNC hold from HSYNC falling edge Tf2hhold HBPD + HFPD +
HOZVAL + 3
- - Pvclk
NOTES:
1. VCLK period
2. HSYNC period
Table 29-14. IIS Controller Module Signal Timing Constants(I2S Master Mode Only)
(VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = –40 to 85 °C, VDD_OP2 = 3.3V ± 0.3V)
Parameter Symbol Min. Typ. Max Unit
LR Clock Input Delay
T
LRId
5 - 13 ns
Serial Data Setup Time
T
DS
10 - ns
Serial Data Hold Time
T
DH
10 - ns