User's Manual

S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA
29-23
Table 29-8. Clock Timing Constants
(VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), T
A
= -40 to 85°C, VDD_OP1 = 3.3V ± 0.3V)
Parameter Symbol Min Typ Max Unit
Crystal clock input frequency
f
XTAL
10 - 30 MHz
Crystal clock input cycle time
t
XTALCYC
33 - 100 ns
External clock input frequency
(note 1)
f
EXT
10 133 MHz
External clock input cycle time
(note 1)
t
EXTCYC
7.5 100 ns
External clock input low level pulse width
t
EXTLOW
3.5 - ns
External clock input high level pulse width
t
EXTHIGH
3.5 - ns
External clock to HCLK (without PLL)
t
EX2HC
5 13 ns
HCLK (internal) to CLKOUT
t
HC2CK
3.3 8.8 ns
HCLK (internal) to SCLK
t
HC2SCLK
1.9 5.8 ns
Reset assert time after clock stabilization
t
RESW
4 - XTIpll or
EXTCLK
PLL Lock Time
t
PLL
300 - us
Sleep mode return oscillation setting time.
(note 2)
t
OSC2
2 524290 XTIpll or
EXTCLK
The interval before CPU runs after nRESET is
released.
t
RST2RUN
5 - XTIpll or
EXTCLK
NOTES:
1. If does not use MPLL, External clock input range is 10MHz ~ 133MHz but if use MPLL , External clock input range is
10MHz ~ 30MHz
2. t
OSC2
is programmable by setting the PWRSETCNT bits in Reset Count register.
t
OSC2
= (PWRSETCNT+1) * 2048