User's Manual

S3C2450X RISC MICROPROCESSOR PCM AUDIO INTERFACE
28-7
PCM_CTLn Bit Description Initial State
DMA_RX request will occur whenever the RXFIFO is not
empty.
TX_MSB_POS [4] Controls the position of the MSB bit in the serial output
stream relative to the PCMFSYNC signal
0 = MSB sent during the same clock that PCMFSYNC is high
1 = MSB sent on the next PCMSCLK cycle after
PCMFSYNC is high
0
RX_MSB_POS [3] Controls the position of the MSB bit in the serial input stream
relative to the PCMFSYNC signal
0 = MSB is captured on the falling edge of PCMSCLK during
the same cycle that PCMFSYNC is high
1 = MSB is captured on the falling edge of PCMSCLK during
the cycle after the PCMFSYNC is high
0
PCM_TXFIFO_EN [2]
Enable the TXFIFO
(note 1)
0
PCM_RXFIFO_EN [1]
Enable the RXFIFO
(note 1)
0
PCM_PCM_ENABL
E
[0] PCM enable signal.
1 = Enables the serial shift state machines.
(note 2)
The enable must be set HIGH for the PCM to operate.
0 = The PCMSOUT will not toggle.
The internal divider-counters (serial shift register’s counter)
are held in reset.
(note 3)
0
NOTES:
1. To flush FIFO, first set PCM_TX/RXFIFO_EN =0x0 then set PCM_TX/RXFIFO_EN =0x1.
2. To Start PCM operation please refer the following steps
- PCM_TXFIFO_EN=0x1;
- PCM_TX_DMA_EN=0x1;
- wait until fifo full
- CTL_SERCLK_EN =0x1;
- PCM_PCM_ENABLE = 0x1;
3. To pause PCM operation, with CTL_SERCLK_EN = 0x0, PCM_PCM_ENABLE bit should be set to zero.