User's Manual

S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER
27-15
8.5 AC97 CODEC STATUS REGISTER (AC_CODEC_STAT)
If the Read enable bit is 1 and Codec command address is valid, Codec status data is also valid.
Register Address R/W Description Reset Value
AC_CODEC_STAT 0x5B00000C R AC97 Codec Status Register 0x00000000
AC_CODEC_STAT Bit Description Initial State
-
[31:23]
Reserved.
0x00
Address
[22:16]
Codec status address
0x00
Data
[15:0]
Codec status data
0x0000
NOTES: If you want to read data from AC97 codec register via the AC_CODDEC_STAT register, you should follow the steps.
1. Write command address and data on the AC_CODEC_CMD register with Bit[23] =1.
2. Have a delay time.
3. Read command address and data from AC_CODEC_STAT register.
8.6 AC97 PCM OUT/IN CHANNEL FIFO ADDRESS REGISTER (AC_PCMADDR)
To index the internal PCM FIFOs address.
Register Address R/W Description Reset Value
AC_PCMADDR 0x5B000010 R AC97 PCM Out/In Channel FIFO Address Register 0x00000000
AC_PCMADDR Bit Description Initial State
- [31:28] Reserved. 0000
Out read address [27:24] PCM out channel FIFO read address 0000
- [23:20] Reserved. 0000
In read address [19:16] PCM in channel FIFO read address 0000
- [15:12] Reserved. 0000
Out write address [11:8] PCM out channel FIFO write address 0000
- [7:4] Reserved. 0000
In write address [3:0] PCM in channel FIFO write address 0000