User's Manual

AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR
27-14
8.3 AC97 GLOBAL STATUS REGISTER (AC_GLBSTAT)
This is the status register. When the interrupt is occurred, you can check what the interrupt source is.
Register Address R/W Description Reset Value
AC_GLBSTAT 0x5B000004 R AC97 Global Status Register 0x00000001
AC_GLBSTAT Bit Description Initial State
- [31:23] Reserved.
0x00
Codec ready interrupt [22] 0 = Not requested 1 = Requested
0
PCM out channel underrun
interrupt
[21]
0 = Not requested 1 = Requested
0
PCM in channel overrun interrupt [20] 0 = Not requested 1 = Requested
0
MIC in channel overrun interrupt [19] 0 = Not requested 1 = Requested
0
PCM out channel threshold
interrupt
[18]
0 = Not requested 1 = Requested
0
PCM in channel threshold
interrupt
[17]
0 = Not requested 1 = Requested
0
MIC in channel threshold
interrupt
[16]
0 = Not requested 1 = Requested
0
- [15:3] Reserved.
0x000
Controller main state [2:0] 000 = Idle 001 = Init 010 = Ready
011 = Active 100 = LP 101 = Warm
001
8.4 AC97 CODEC COMMAND REGISTER (AC_CODEC_CMD)
When you control writing or reading, you must set the Read enable bit, If you want to write data to the AC97
Codec, you set the index(or address) of the AC97 Codec and data.
Register Address R/W Description Reset Value
AC_CODEC_CMD 0x5B000008 R/W AC97 Codec Command Register 0x00000000
AC_CODEC_CMD Bit Description Initial State
-
[31:24]
Reserved
0x00
Read enable
[23]
0 = Command write
(note)
1 = Status read
0
Address
[22:16]
Codec command address
0x00
Data
[15:0]
Codec command data
0x0000
NOTE: When the commands are written on the AC_CODDEC_CMD register, It is recommended that the delay time between
the command and the next command is more than 1 / 48kHz.