User's Manual

S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER
27-9
5 AC97 POWER-DOWN
For details, please refer the AC-Link Power Managerment part of AC97 revision 2.0 specification.
SDATA_OUT
SDATA_IN
BIT_CLK
SYNC
slot 12
prev.frame
Write to
0X26
slot 12
prev.frame
TAG
TAG
Data
PR4
Figure 27-7. AC97 Power-down Timing
5.1.1 Powering Down the AC-link
The AC-link signals enter a low power mode when the AC97 Codec Power-down register (0x26) bit PR4 is set to
a 1 (by writing 0x1000). Then the Primary Codec drives both BITCLK and SDATA_IN to a logic low voltage level.
The sequence follows the timing diagram shown in Figure 27-7.
The AC97 Controller transmits the write to Power-down register (0x26) over the AC-link. Set up the AC97
Controller so that it does not transmit data to slots 3-12 when it writes to the Power-down register bit PR4 (data
0x1000), and it does not require the Codec to process other data when it receives a power down request. When
the Codec processes the request it immediately transitions BITCLK and SDATA_IN to a logic low level. The AC97
Controller drives SYNC and SDATA_OUT to a logic low level after programming the AC_GLBCTRL register.
5.1.2 Waking up the AC-link - Wake Up Triggered by the AC97 Controller
AC-link protocol provides for a cold AC97 reset and a warm AC97 reset. The current power-down state ultimately
dictates which AC97 reset is used. Registers must stay in the same state during all power-down modes unless a
cold AC97 reset is performed. In a cold AC97 reset, the AC97 registers are initialized to their default values. After
a power down, the AC-link must wait for a minimum of four audio frame times after the frame in which the power
down occurred before it can be reactivated by reasserting the SYNC signal. When AC-link powers up, it indicates
readiness through the Codec ready bit (input slot 0, bit 15).