User's Manual

S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR
26-16
8.1 IIS CONTROL REGISTER (IISCON)
Register Address Description Reset Value
IISCON 0x55000000 IIS interface control register 0x0000_C600
IISCON Bit R/W Description
Reserved [31:18] R/W
Reserved. Program to zero.
FTXURSTATUS [17] R/W
TX FIFO under-run interrupt status. And this is used by interrupt clear
bit. When this is high, you can do interrupt clear by writing ‘1’.
0 = Interrupt didn’t be occurred.
1 = Interrupt was occurred.
FTXURINTEN [16] R/W
TX FIFO Under-run Interrupt Enable
0 = TXFIFO Under-run INT disable
1 = TXFIFO Under-run INT enable 1)
FTX2EMPT [15] R
TX FIFO2 empty Status Indication
0 = TX FIFO2 is not empty(Ready to transmit Data)
1 = TX FIFO2 is empty (Not Ready to transmit Data)
FTX1EMPT [14] R
TX FIFO1 empty Status Indication
0 = TX FIFO1 is not empty(Ready to transmit Data)
1 = TX FIFO1 is empty (Not Ready to transmit Data)
FTX2FULL [13] R
TX FIFO2 full Status Indication
0 = TX FIFO2 is not full
1 = TX FIFO2 is full
FTX1FULL [12] R
TX FIFO1 full Status Indication
0 = TX FIFO1 is not full
1 = TX FIFO1 is full
LRI [11] R
Left/Right channel clock indication. Note that LRI meaning is
dependent on the value of LRP bit of I2SMOD register.
0 = Left (when LRP bit is low) or right (when LRP bit is high)
1 = Right (when LRP bit is low) or left (when LRP bit is high)
FTX0EMPT [10] R
Tx FIFO0 empty status indication.
0 = FIFO is not empty (ready for transmit data to channel)
1 = FIFO is empty (not ready for transmit data to channel)
FRXEMPT [9] R
Rx FIFO empty status indication.
0 = FIFO is not empty
1 = FIFO is empty
FTX0FULL [8] R
Tx FIFO0 full status indication.
0 = FIFO is not full
1 = FIFO is full