User's Manual

IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR
25-20
8.3 IIS FIFO CONTROL REGISTER (IISFIC)
Register Address Description Reset Value
IISFIC 0x55000108 IIS interface FIFO control register 0x0000_0000
IISFIC Bit R/W Description
[31:16] R/W
Reserved. Program to zero.
TFLUSH [15] R/W
TX FIFO flush command.
0 = No flush
1 = Flush
[14:13] R/W
Reserved. Program to zero.
FTXCNT [12:8] R
TX FIFO data count. (0~16)
RFLUSH [7] R/W
RX FIFO flush command.
0 = No flush
1 = Flush
[6:5] R/W
Reserved. Program to zero.
FRXCNT [4:0] R
RX FIFO data count. (0~16)
NOTE: Tx FIFOs, Rx FIFO has 32-bit width and 16 depth structure, so FIFO data count value ranges from 0 to 16.
8.4 IIS PRESCALER CONTROL REGISTER (IISPSR)
Register Address Description Reset Value
IISPSR 0x5500010C IIS interface clock divider control register 0x0000_0000
IISPSR Bit R/W Description
[31:16] R/W
Reserved. Program to zero.
PSRAEN [15] R/W Pre-scaler (Clock divider) active.
1 = Active (divide I2SAudioCLK with Pre-scaler division value)
0 = Inactive (bypass I2SAudioCLK) (Refer to Figure 25-2)
[14] R/W Reserved. Program to zero.
PSVALA [13:8] R/W Pre-scaler (Clock divider) division value.
N = Division factor is N+1 (1~1/64)
[7:0] R/W Reserved. Program to zero.