User's Manual

S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE
25-17
IISCON Bit R/W Description
RXDMAPAUSE [5] R/W
Rx DMA operation pause command. Note that when this bit is activated
at any time, the DMA request will be halted after current on-going DMA
transfer is completed.
0 = No pause DMA operation
1 = Pause DMA operation
TXCHPAUSE [4] R/W
Tx channel operation pause command. Note that when this bit is
activated at any time, the channel operation will be halted after left-right
channel data transfer is completed.
0 = No pause operation
1 = Pause operation
RXCHPAUSE [3] R/W
Rx channel operation pause command. Note that when this bit is
activated at any time, the channel operation will be halted after left-right
channel data transfer is completed.
0 = No pause operation
1 = Pause operation
TXDMACTIVE [2] R/W
Tx DMA active (start DMA request). Note that when this bit is set from
high to low, the DMA operation will be forced to stop immediately.
0 = Inactive
1 = Active
RXDMACTIVE [1] R/W
Rx DMA active (start DMA request). Note that when this bit is set from
high to low, the DMA operation will be forced to stop immediately.
0 = Inactive
1 = Active
I2SACTIVE [0] R/W
IIS interface active (start operation).
0 = Inactive
1 = Active
NOTE: When playing is finished, Under-run interrupt will be occurring. (Since no more data are written into TXFIFO at the end
of playing.) User can stop transmission at this Under-run interrupt.