User's Manual

IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR
25-16
8.1 IIS CONTROL REGISTER (IISCON)
Register Address Description Reset Value
IISCON 0x55000100 IIS interface control register 0x0000_0600
IISCON Bit R/W Description
[31:18] R/W
Reserved. Program to zero.
FTXURSTATUS [17] R/W
TX FIFO under-run interrupt status. And this is used by interrupt clear
bit. When this is high, you can do interrupt clear by writing ‘1’.
0 = Interrupt didn’t be occurred.
1 = Interrupt was occurred.
FTXURINTEN [16] R/W
TX FIFO Under-run Interrupt Enable
0 = TXFIFO Under-run INT disable
1 = TXFIFO Under-run INT enable1)
[15:12] R/W
Reserved. Program to zero.
LRI [11] R
Left/Right channel clock indication. Note that LRI meaning is dependent
on the value of LRP bit of I2SMOD register.
0 = Left (when LRP bit is low) or right (when LRP bit is high)
1 = Right (when LRP bit is low) or left (when LRP bit is high)
FTXEMPT [10] R
Tx FIFO empty status indication.
0 = FIFO is not empty (ready for transmit data to channel)
1 = FIFO is empty (not ready for transmit data to channel)
FRXEMPT [9] R
Rx FIFO empty status indication.
0 = FIFO is not empty
1 = FIFO is empty
FTXFULL [8] R
Tx FIFO full status indication.
0 = FIFO is not full
1 = FIFO is full
FRXFULL [7] R
Rx FIFO full status indication.
0 = FIFO is not full (ready for receive data from channel)
1 = FIFO is full (not ready for receive data from channel)
TXDMAPAUSE [6] R/W
Tx DMA operation pause command. Note that when this bit is activated
at any time, the DMA request will be halted after current on-going DMA
transfer is completed.
0 = No pause DMA operation
1 = Pause DMA operation