User's Manual

S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE
25-7
6.4 SAMPLING FREQUENCY AND MASTER CLOCK
Master clock frequency (RCLK) can be selected by sampling frequency as shown in Table 25-1. Because RCLK
is made by IIS pre-scaler, the pre-scaler value and RCLK type (256fs or 384fs or 512fs or 768fs) should be
determined properly.
Table 25-1. CODEC clock (CODECLK = 256fs, 384fs, 512fs, 768fs)
IISLRCK
(fs)
8.000
kHz
11.025
kHz
16.000
kHz
22.050
kHz
32.000
kHz
44.100
kHz
48.000
kHz
64.000
kHz
88.200
kHz
96.000
kHz
256fs
2.0480 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760
384fs
CODECLK
3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640
(MHz)
512fs
4.0960 5.6448 8.1920 11.2900 16.3840 22.5790 24.5760 32.7680 45.1580 49.1520
768fs
6.1440 8.4672 12.2880 16.9340 24.5760 33.8690 36.8640
49.1520 - -
NOTE: fs represents sampling frequency.
CODECLK Frequency = fs * (256 or 384 or 512 or 768)
6.5 IIS CLOCK MAPPING TABLE
On selecting BFS, RFS, and BLC bits of I2SMOD register, user should refer to the following table. Table 25-2
shows the allowable clock frequency mapping relations.
Table 25-2. IIS Clock Mapping Table
RFS
Clock Frequency
256 fs (00B) 512 fs (01B) 384 fs (10B) 768 fs (11B)
16 fs (10B)
(a) (a) (a) (a)
24 fs (11B)
- - (a) (a)
32 fs (00B)
(a) (b) (a) (b) (a) (b) (a) (b)
BFS
48 fs (01B)
- - (a) (b) (c) (a) (b) (c)
Descriptions
(a) Allowed when BLC is 8-bit (01B)
(b) Allowed when BLC is 16-bit (00B)
(c) Allowed when BLC is 24-bit (10B)
NOTE: Bit Clock Frequency ≥ fs * (bit length * 2). Under this condition Bit Clock Frequency can be one of among fs * (16 or
24 or 32 or 48). The codec clock is a multiple of the bit clock among fs * (256 or 384 or 512 or 768)
Example : If bit length is 16 bit, Bit Clock Frequency ≥ fs * 32. So it can be one of fs * (32 or 48).
If Bit Clock Frequency is 48 fs, then 384fs(48 fs* 8) and 768fs(48 fs * 16) are the clock which is a
multiple of the Bit Clock Frequency.