User's Manual

CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR
23-38
6.36 IMAGE CAPTURE ENABLE REGISTER
Register Address R/W Description Reset Value
CIIMGCPT 0x4D80_00A0 RW Image capture enable command 0
CIIMGCPT Bit Description
Initial
State
Change
State
ImgCptEn [31] camera interface global capture enable 0 O
ImgCptEn_
CoSc
[30] capture enable for codec scaler. This bit must be zero in
scaler-bypass mode.
0 O
ImgCptEn_
PrSc (v)
[29] capture enable for preview scaler. (applied both Memory
data input path and External camera path in using preview)
This bit must be zero in scaler-bypass mode.
0 O
Reserved [28:27] 0 X
Cpt_CoDMA_
Sel
[26] Codec DMA output format
1 = RGB 16/24 bit (Must be Out422_Co=1 ,
Interleave_Co=1)
0 = YCbCr 4:2:2 or 4:2:0
0 O
Cpt_CoDMA_
RGBFMT
[25] Codec DMA RGB format
1 = RGB 24-bit
0 = RGB 16-bit
0 O
Cpt_CoDMA_
En
[24] Capture codec dma frame control. It is also used for start
signal of Codec image capture. Therefore, it must be set to
‘1’ if codec image is wanted. or it must be set to ‘0’ if codec
image is not captured.
1 = Enable
0 Disable
0 X
Cpt_CoDMA_
Ptr
[23:19] Capture sequence turn-around pointer 0 X
Cpt_CoDMA_
Mod
[18] Capture codec dma mode
1 = Apply Cpt_CoDMA_Cnt mode (capture
Cpt_CoDMA_Cnt frames along the Cpt_CoDMA_Seq after
Cpt_CoDMA_En becomes high)
0 = Apply Cpt_CoDMA_En mode (capture frames along the
Cpt_CoDMA_Seq during Cpt_CoDMA_En is high)
0 X
Cpt_CoDMA_
Cnt
[17:10] Wanted number of frames to be captured (when read, you
will see the value of a shadow register which is
downcounted when a frame is captured. That is,
Cpt_CoDMA_Cnt has an initially loaded value still after a
frame is captured.)
0 X
Reserved [9:0] 0 X