User's Manual

S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE
23-31
6.24 CODEC STATUS REGISTER
Register Address R/W Description Reset Value
CICOSTATUS 0x4D80_0064 R Codec path status 0
CICOSTATUS Bit Description
Initial
State
Change
State
OvFiY_Co [31] Overflow state of codec FIFO Y 0 X
OvFiCb_Co [30] Overflow state of codec FIFO Cb 0 X
OvFiCr_Co [29] Overflow state of codec FIFO Cr 0 X
VSYNC
[28] Camera VSYNC (This bit can be referred by CPU for first
SFR setting after external camera muxing. And, it can be
seen in the ITU-R BT 656 mode)
0 X
FrameCnt_Co
[27:26] Frame count of codec DMA (This counter value means the
next frame number)
0 X
WinOfstEn_Co [25] Window offset enable status 0 X
FlipMd_Co [24:23] Flip mode of codec DMA 0 X
ImgCptEn_
CamIf
[22] Image capture enable of camera interface 0 X
ImgCptEn_
CoSC
[21] Image capture enable of codec path 0 X
VSYNC
[20] External camera VSYNC (polarity inversion was not
adopted.)
X X
Reserved [9:1] Reserved 0 X
FIELD [0] Camera FIELD(polarity inversion was adopted) 0 X
6.25 RGB1 START ADDRESS REGISTER
Register Address R/W Description Reset Value
CIPRCLRSA1
0x4D80_006C RW
RGB 1
st
frame start address for preview DMA
0
CIPRCLRSA1 Bit Description
Initial
State
Change
State
CIPRCLRSA1 (v)
[31:0]
RGB 1
st
frame start address for preview DMA
0 X