User's Manual

CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR
23-30
6.22 CODEC MAIN-SCALER CONTROL REGISTER
Register Address R/W Description Reset Value
CICOSCCTRL 0x4D80_0058 RW Codec main-scaler control 0
CICOSCCTRL Bit Description
Initial
State
Change
State
ScalerBypass_Co
[31] Codec scaler bypass for upper 2048 x 2048 size (In this
case, ImgCptEn_CoSC and ImgCptEn_PrSC should be 0,
but ImgCptEn should be 1. It is not allowed to capturing
preview image. This mode is intended to capture JPEG
input image for DSC application) In this case, input pixel
buffering depends on only input FIFOs, so system bus
should be not busy in this mode.
0 O
ScaleUp_H_Co
[30] Horizontal scale up/down flag for codec scaler (In 1:1
scale ratio, this bit should be “1”) 1: up, 0:down
0 O
ScaleUp_V_Co
[29] Vertical scale up/down flag for codec scaler (In 1:1 scale
ratio, this bit should be “1”) 1: up, 0:down
0 O
Reserved [28:25] 0 X
MainHorRatio_Co [24:16] Horizontal scale ratio for codec main-scaler 0 O
CoScalerStart [15] Codec scaler start 0 O
Reserved [14:9] 0 X
MainVerRatio_Co [8:0] Vertical scale ratio for codec main-scaler 0 O
6.23 CODEC DMA TARGET AREA REGISTER
Register Address R/W Description Reset Value
CICOTAREA 0x4D80_005C RW Codec pre-scaler destination format 0
CICOTAREA Bit Description
Initial
State
Change
State
Reserved [31:26] 0 X
CICOTAREA
[25:0] Target area for codec DMA
= Target H size x Target V size
0 X