User's Manual

S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE
23-17
6.3 GLOBAL CONTROL REGISTER
Register Address R/W Description Reset Value
CIGCTRL 0x4D80_0008 RW Global control register 2000_0000
CIGCTRL Bit Description
Initial
State
Change
State
SwRst
[31] Camera interface software reset. Before setting this bit, you
should set the ITU601_656n bit of CISRCFMT as “1”
temporarily at first SFR setting. Next sequence is
recommended.
(ITU601 case : ITU601_656n “1” → SwRst “1” → SwRst “0”
for first SFR setting ,
ITU656 case : ITU601_656n “1” → SwRst “1” → SwRst “0”
→ ITU601_656n “0” for first SFR setting)
0 X
CamRst [30] External camera processor Reset or Power Down control 0 X
Reserved [29] Must be 1 1 X
TestPattern
[28:27] This register should be set at only ITU-T 601 8-bit mode. Not
allowed with ITU-T 656 mode. (max. 1280 X 1024)
00 = external camera processor input (normal)
01 = color bar test pattern
10 = horizontal increment test pattern
11 = vertical increment test pattern
0 X
InvPolPCLK [26] 1 = inverse the polarity of PCLK 0 = normal 0 X
InvPolVSYNC [25] 1 = inverse the polarity of VSYNC 0 = normal 0 X
InvPolHREF [24] 1 = inverse the polarity of HREF 0 = normal 0 X
Non-use [23] 0 X
IRQ_Ovfen
[22] 1 = Overflow interrupt enable (Interrupt is generated during
overflow occurrence)
0 = Overflow interrupt disable (normal)
0 X
Href_mask
[21] 1 = mask out Href during Vsync high
0 = no mask
0 X
Reserved [20:0] 0 X
FIELDMODE [2]
ITU601 Interlace field port mode enable (don’t care this bit in
itu656). This bit should be connected with FIELD signal
1 = FIELD port enable 0 = disable
0 X
InvPolFIELD [1] 1 = inverse the polarity of FIELD 0 = normal 0 X
Cam_Interlace [0]
External camera data transmission mode
1 = Interlace 0 = Progressive
0 X