User's Manual

PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR
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Signal In/Out Description
DN IO
DATA(–) from USB host. (Need to 15kΩ pull-down)
DP IO
DATA(+) from USB host. (Need to 15kΩ pull-down)
USB Device
DM_UDEV IO DATA(–) for USB peripheral.
DP_UDEV IO DATA(+) for USB peripheral.
REXT O External Resistor ( 44.2ohm +/- 1%)
XO_UDEV OSC Crystal output
XI_UDEV OSC Crystal input
SPI
SPIMISO[1:0] IO SPIMISO is the master data input line, when SPI is configured as a
master.
When SPI is configured as a slave, these pins reverse its role.
SPIMOSI[1:0] IO SPIMOSI is the master data output line, when SPI is configured as a
master.
When SPI is configured as a slave, these pins reverse its role.
SPICLK[1:0] IO SPI clock
nSS[1:0] I SPI chip select (only for slave mode)
SDMMC Interface
SD1_DAT[7:0] IO SD1 receive/transmit data
SD1_CMD IO SD1 receive response/ transmit command
SD1_CLK O SD1 clock
SD1_nWP O SD1 Write Protect
SD1_nCD O SD1 Card Detect
SD1_nLED O SD1 LED
SD0_DAT[3:0] IO SD0 receive/transmit data
SD0_CMD IO SD0 receive response/ transmit command
SD0_CLK O SD0 clock
General Port
GPn[173:0] IO General input/output ports, which are multiplexed with other function pins
(some ports are output only).
TIMMER/PWM
TOUT[3:0] O Timer output[3:0]
TCLK I External timer clock input
JTAG TEST LOGIC
nTRST I nTRST (TAP Controller Reset) resets the TAP controller at start.
If debugger is used, A 10K pull-up resistor has to be connected.
If debugger (black ICE) is not used, nTRST pin must be issued by a low
active pulse (Typically connected to nRESET).
TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP
controller's states.