User's Manual

S3C2450X RISC MICROPROCESSOR LCD CONTROLLER
22-35
8.1.4 Video Main Control 1 Register
Register Address R/W Description Reset Value
VIDCON1 0x4C800004 R/W Video control 2 register 0x0000_0000
VIDCON1 Bit Description Initial state
LINECNT
(read only)
[26:16] Provide the status of the line counter (read only)
Up count from 0 to LINEVAL
0
Reserved [15] Reserved 0
VSTATUS [14:13] Vertical Status (read only).
00 = VSYNC 01 = BACK Porch
10 = ACTIVE 11 = FRONT Porch
0
HSTATUS [12:11] Horizontal Status (read only).
00 = HSYNC 01 = BACK Porch
10 = ACTIVE 11 = FRONT Porch
0
Reserved [10:8] Reserved
IVCLK [7] This bit controls the polarity of the VCLK active edge.
0 = The video data is fetched at VCLK falling edge
1 = The video data is fetched at VCLK rising edge
0
IHSYNC [6] This bit indicates the HSYNC pulse polarity.
0 = normal(active high) 1 = inverted(active low)
0
IVSYNC [5] This bit indicates the VSYNC pulse polarity.
0 = normal(active high) 1 = inverted(active low)
0
IVDEN [4] This bit indicates the VDEN signal polarity.
0 = normal(active high) 1 = inverted(active low)
0
Reserved [3:0] Reserved 0x0
8.1.5 VIDEO Time Control 0 Register
Register Address R/W Description Reset Value
VIDTCON0 0x4C800008 R/W Video time control 1 register 0x0000_0000
VIDTCON0 Bit Description Initial State
VBPD [23:16] Vertical back porch is the number of inactive lines at the start of a
frame, after vertical synchronization period. (Period : VBPD +1)
0x00
VFPD [15:8] Vertical front porch is the number of inactive lines at the end of a
frame, before vertical synchronization period. (Period : VFPD +1)
0x00
VSPW [7:0] Vertical sync pulse width determines the VSYNC pulse's level
width by counting the number of inactive lines.
(Period : VSPW +1)
0x00