User's Manual

PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR
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Signal In/Out Description
RGB_VCLK/SYS_WR O RGB I/F LCD Clock
i80 I/F Write Enable
RGB_VSYNC/SYS_CS1 O RGB I/F Vertical Sync. Signal
i80 I/F Sub LCD Select
RGB_HSYNC/SYS_CS0 O RGB I/F Horizontal Sync. Signal
i80 I/F Main LCD Select
RGB_VDEN/SYS_RS O RGB I/F Data Enable
i80 I/F Register/ State select
RGB_LEND/SYS_OE O RGB I/F Line End Signal
i80 I/F Output Enable
CAMERA Interface
CAMRESET O Camera interface reset
CAMCLKOUT O Camera interface master clock
CAMPCLK I Camera interface pixel clock
CAMHREF I Camera interface horizontal sync
CAMVSYNC I Camera interface horizontal sync
CAMDATA[7:0] I Camera interface data
CAM_FIELD_A I Interlace field (only used in interlace mode)
Interrupt Control Unit
EINT[23:0] I External interrupt request
External I/F
nXDREQ[1:0] I External DMA request
nXDACK[1:0] O External DMA acknowledge
nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request
control of the local bus. nXBACK active indicates that bus control has
been granted.
nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C2450 has
surrendered control of the local bus to another bus master.
UART
RXD[3:0] I UART receives data input (ch. 0/1/2)
TXD[3:0] O UART transmits data output (ch. 0/1/2)
nCTS[2:0] I UART clear to send input signal (ch. 0/1)
nRTS[2:0] O UART request to send output signal (ch. 0/1)
EXTUARTCLK I External clock input for UART
TSADC
AIN[9:0] AI ADC input [9:0]. If do not use ADC function, AIN [9] and AIN [7] pins are
tied to VDDA_ADC. Others are tied to GND.
When touch screen device is used, A[6], A[7] , A[8] and A[9] are used as
YM, YP, XM and XP, respectively.