User's Manual

iv S3C2450X RISC MICROPROCESSOR
Table of Contents (Continued)
Chapter 2 System Controller (Continued)
8 Individual Register Descriptions................................................................................................................2-22
8.1 Clock Source Control Registers
(LOCKCON0, LOCKCON1, OSCSET, MPLLCON, and EPLLCON) ..............................................2-22
8.2 Clock Control Register (CLKSRC, CLKDIV, HCLKCON, PCLKCON, and SCLKCON).................2-25
8.3 Power Management Registers (PWRMODE and PWRCFG) .........................................................2-31
8.4 Reset Control Registers (SWRST and RSTCON)...........................................................................2-33
8.5 Control of retention PAD(I/O) when normal mode and wake-up from sleep mode.........................2-34
8.6 System Controller Status Registers (WKUPSTAT and RSTSTAT).................................................2-35
8.7 Bus Configuration Register (BUSPRI0, BUSPRI1, and BUSMISC)................................................2-36
8.8 Information Register 0,1,2,3 ............................................................................................................2-37
8.9 USB PHY Control register (PHYCTRL) ...........................................................................................2-38
8.10 USB PHY Power Control Register (PHYPWR) .............................................................................2-39
8.11 USB Reset Control Register (URSTCON).....................................................................................2-39
8.12 USB Clock Control Register (UCLKCON) .....................................................................................2-40
Chapter 3 Bus Matrix & EBI
1 Overview....................................................................................................................................................3-1
2 Special Function Registers .......................................................................................................................3-2
2.1 Matrix Core 0 Priority Register (Bpriority0)......................................................................................3-2
2.2 Matrix Core 1 Priority Register (Bpriority1)......................................................................................3-2
2.3 EBI Control Register (EBICON).......................................................................................................3-3
Chapter 4 Bus Priorities
1 Overview....................................................................................................................................................4-1
1.1 Bus Priority MAP..............................................................................................................................4-1