User's Manual

PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR
1-24
4.1 SIGNAL DESCRIPTIONS
Table 1-4. S3C2450 Signal Descriptions
Signal In/Out Description
Reset, Clock & Power
XTIpll AI Crystal input signals for internal osc circuit.
When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK
source.
If it isn't used, it has to be Low (0V)
XTOpll AO Crystal output signals for internal osc circuit.
When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK
source. If it isn't used, it has to be float
NC AI Not connected.
EPLLCAP AI Loop filter capacitor for Extra PLL
XTIrtc AI 32.768 kHz crystal input for RTC. If it isn’t used, it has to be High
(VDD_RTC=3.3V).
XTOrtc AO 32.768 kHz crystal output for RTC. If it isn’t used, it has to be float.
CLKOUT[1:0] O Clock output signal. The CLKSEL of MISCCR(GPIO register) register
configures the clock output mode among the MPLL_CLK, EPLL CLK,
ARMCLK, HCLK, PCLK.
nRESET ST nRESET suspends any operation in progress and places S3C2450 into a
known reset state. For a reset, nRESET must be held to L level for at
least 4 OSCin after the processor power has been stabilized.
nRSTOUT O For external device reset control (nRSTOUT = nRESET & nWDTRST &
SW_RESET) *SW_RESET = nRSTCON of GPIO MISCCR
PWREN O core power on-off control signal
nBATT_FLT I Probe for battery state (Does not wake up at Sleep mode in case of low
battery state). If it isn’t used, it has to be High (3.3V).
OM[4:0] I OM[4:0] set operating modes of S3C2450
Refer to “S3C2450 Operation Mode Description Table”
EXTCLK I External clock source.
When OM[0] = 1, EXTCLK is used for MPLL and EPLL CLK source.
If it isn't used, it has to be Low (0V).
Memory Interface (ROM/SRAM/NAND/CF)
RADDR[25:0] O RADDR[25:0] (Address Bus) outputs the memory address of the
corresponding bank .
RDATA[15:0] IO RDATA[15:0] (Data Bus) inputs data during memory read and outputs
data during memory write. The bus width is programmable among 8/16-
bit.
nRCS[5:0] O nRCS[5:0] (Chip Select) are activated when the address of a memory is
within the address region of each bank. The number of access cycles and
the bank size can be programmed.
nRWE O nRWE (Write Enable) indicates that the current bus cycle is a write cycle.
nROE O nOE (Output Enable) indicates that the current bus cycle is a read cycle.