User's Manual

HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR
21-64
5.27 CONTROL REGISTER 2
Register Address R/W Description Reset Value
CONTROL2_0 0X4AC00080 R/W Control register 2 (Channel 0) 0x0
CONTROL2_1 0X4A800080 R/W Control register 2 (Channel 1) 0x0
Name Bit Description Initial Value
[31]
Write Status Clear Async Mode Enable
This bit can make async-clear enable about Normal and Error
interrupt status bit. During the initialization procedure
command operation, this bit should be enabled.
0 = Disable
1 = Enable
0
CDINVRXD3 [30]
Command Conflict Mask Enable
This bit can mask enable the Command Conflict Status (bit
[1:0] of the “ERROR INTERRUPT STATUS REGISTER”)
0 = Mask Disable
1 = Mask Enable
0
CDINVRXD3 [29]
Card Detect signal inversion for RX_DAT[3]
0 = Disable
1 = Enable
0
SELCARDOUT [28]
Card Removed Condition Selection
0 = Card Removed condition is “Not Card Insert” State (When
the transition from “Card Inserted” state to “Debouncing”
state)
1 = Card Removed state is “Card Out” State (When the
transition from “Debouncing state to “No Card” state)
0
FLTCLKSEL [27:24]
Filter Clock (iFLTCLK) Selection
Filter Clock period = 2^(FltClkSel + 5) x iSDCLK period
0000 = 25 x iSDCLK, 0001 = 26 x iSDCLK … 1111 = 220 x
iSDCLK
0
LVLDAT [23:16]
DAT line level
Bit[23]=DAT[7], BIT[22]=DAT[6], BIT[21]=DAT[5],
BIT[20]=DAT[4],
Bit[19]=DAT[3], BIT[18]=DAT[2], BIT[17]=DAT[1],
BIT[16]=DAT[0]
(Read Only)
Line state
ENFBCLKTX [15]
Feedback Clock Enable for Tx Data/Command Clock
0 = Disable
1 = Enable
0
ENFBCLKRX [14]
Feedback Clock Enable for Rx Data/Command Clock
0 = Disable
1 = Enable
0
SDCDSEL [13]
SD Card Detect Signal Selection
0