User's Manual

S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER
21-41
5.15 CLOCK CONTROL REGISTER
At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency Select according to the
Capabilities register.
Register Address R/W Description Reset Value
CLKCON0 0X4AC0002C R/W Command Register (Channel 0) 0x0
CLKCON1 0X4A80002C R/W Command Register (Channel 1) 0x0
Name Bit Description Initial Value
SELFREQ [15:8]
SDCLK Frequency Select
This register is used to select the frequency of SDCLK pin. The
frequency is not programmed directly; rather this register holds the
divisor of the Base Clock Frequency For SD Clock in the
Capabilities register. Only the following settings are allowed.
80h base clock divided by 256
40h base clock divided by 128
20h base clock divided by 64
10h base clock divided by 32
08h base clock divided by 16
04h base clock divided by 8
02h base clock divided by 4
01h base clock divided by 2
00h base clock (10MHz-63MHz)
Setting 00h specifies the highest frequency of the SD Clock. When
setting multiple bits, the most significant bit is used as the divisor. But
multiple bits should not be set. The two default divider values can be
calculated by the frequency that is defined by the Base Clock
Frequency For SD Clock in the Capabilities register.
(1) 25MHz divider value
(2) 400kHz divider value
According to the SD Physical Specification Version 1.01 and the
SDIO Card Specification Version 1.0, maximum SD Clock frequency
is 25MHz, and shall never exceed this limit.
The frequency of SDCLK is set by the following formula:
Clock Frequency = (Base Clock) / divisor
Thus, choose the smallest possible divisor which results in a clock
frequency that is less than or equal to the target frequency.
For example, if the Base Clock Frequency For SD Clock in the
Capabilities register has the value 33MHz, and the target frequency is
25MHz, then choosing the divisor value of 01h will yield 16.5MHz,
which is the nearest frequency less than or equal to the target.
Similarly, to approach a clock value of 400kHz, the divisor value of
40h yields the optimal clock value of 258kHz.
0
[7:4]
Reserved