User's Manual

HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR
21-34
Name Bit Description Initial Value
Changing from 1 to 0 generates a Transfer Complete interrupt in
the Normal Interrupt Status register.
Note: The SD Host Driver can save registers in the range of 000-
00Dh for a suspend transaction after this bit has changed from 1 to
0.
1 = Cannot issue command which uses the DAT line
0 = Can issue command which uses the DAT line
CMDINHCMD [0] Command Inhibit (CMD) (ROC)
If this bit is 0, it indicates the CMD line is not in use and the Host
Controller can issue a SD Command using the CMD line.
This bit is set immediately after the Command register (00Fh) is
written. This bit is cleared when the command response is received.
Even if the Command Inhibit (DAT) is set to 1, Commands using
only the CMD line can be issued if this bit is 0. Changing from 1 to 0
generates a Command
Complete interrupt in the Normal Interrupt Status register. If the
Host Controller cannot issue the command because of a command
conflict error (Refer to Command CRC Error) or because of
Command Not Issued By Auto CMD12 Error, this bit shall remain
1 and the Command Complete is not set. Status issuing Auto
CMD12 is not read from this bit.
1 = Cannot issue command
0 = Can issue command using only CMD line
0
NOTE: Buffer Write Enable in Present register should not be asserted for DMA transfers since it generates Buffer Write
Ready interrupt
Reset
Power ON
Debouncing
Once debouncing
clock becomes valid
Card Inserted
No Card
SDCD=1
SDCD=0
Stable
Stable
Figure 21-13. Card Detect State
The above Figure shows the state definitions of hardware that handles “Debouncing”.