User's Manual

HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR
21-18
5.2 SDMA SYSTEM ADDRESS REGISTER
Register Address R/W Description Reset Value
SYSAD0 0X4AC00000 R/W System Address register (Channel 0) 0x0
SYSAD1 0X4A800000 R/W System Address register (Channel 1) 0x0
This register contains the physical system memory address used for DMA transfers.
Name Bit Description Initial Value
SYSAD [31:0]
SDMA System Address
This register contains the system memory address for a DMA transfer.
When the Host Controller stops a DMA transfer, this register shall point to
the system address of the next contiguous data position. It can be accessed
only if no transaction is executing (i.e., after a transaction has stopped).
Read operations during transfers may return an invalid value.
The Host Driver shall initialize this register before starting a DMA
transaction. After DMA has stopped, the next system address of the next
contiguous data position can be read from this register.
The DMA transfer waits at the every boundary specified by the Host SDMA
Buffer Boundary in the Block Size register. The Host Controller generates
DMA Interrupt to request the Host Driver to update this register. The Host
Driver set the next system address of the next data position to this register.
When the most upper byte of this register (003h) is written, the Host
Controller restarts the DMA transfer. When restarting DMA by the Resume
command or by setting Continue Request in the
Block Gap Control register, the Host Controller shall start at the next
contiguous address stored here in the System Address register.
0x00